[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/InstrSched:

SchedGraph.cpp updated: 1.58 -> 1.59

---
Log message:

Eliminate operator[] is deprecated warnings


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Diffs of the changes:  (+21 -16)

Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.58 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.59
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.58	Fri Feb 13 15:01:20 2004
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp	Wed Feb 18 10:43:51 2004
@@ -53,9 +53,12 @@
 
 SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
                                int   indexInBB, const TargetMachine& Target)
-  : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
-    MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
-  if (MI) {
+  : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(0) {
+  if (mbb) {
+    MachineBasicBlock::iterator I = MBB->begin();
+    std::advance(I, indexInBB);
+    MI = I;
+
     MachineOpCode mopCode = MI->getOpcode();
     latency = Target.getInstrInfo().hasResultInterlock(mopCode)
       ? Target.getInstrInfo().minLatency(mopCode)
@@ -183,11 +186,11 @@
   // Now add CD edges to the first branch instruction in the sequence from
   // all preceding instructions in the basic block.  Use 0 latency again.
   // 
-  for (unsigned i=0, N=MBB.size(); i < N; i++)  {
-    if (&MBB[i] == termMvec[first])   // reached the first branch
+  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
+    if (&*I == termMvec[first])   // reached the first branch
       break;
     
-    SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
+    SchedGraphNode* fromNode = getGraphNodeForInstr(I);
     if (fromNode == NULL)
       continue;			// dummy instruction, e.g., PHI
     
@@ -199,11 +202,11 @@
     // the terminator) that also have delay slots, add an outgoing edge
     // from the instruction to the instructions in the delay slots.
     // 
-    unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
-    assert(i+d < N && "Insufficient delay slots for instruction?");
-      
-    for (unsigned j=1; j <= d; j++) {
-      SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
+    unsigned d = mii.getNumDelaySlots(I->getOpcode());
+
+    MachineBasicBlock::iterator J = I; ++J;
+    for (unsigned j=1; j <= d; j++, ++J) {
+      SchedGraphNode* toNode = this->getGraphNodeForInstr(J);
       assert(toNode && "No node for machine instr in delay slot?");
       (void) new SchedGraphEdge(fromNode, toNode,
                                 SchedGraphEdge::CtrlDep,
@@ -554,10 +557,12 @@
   
   // Build graph nodes for each VM instruction and gather def/use info.
   // Do both those together in a single pass over all machine instructions.
-  for (unsigned i=0; i < MBB.size(); i++)
-    if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
+  unsigned i = 0;
+  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
+       ++I, ++i)
+    if (!mii.isDummyPhiInstr(I->getOpcode())) {
       SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
-      noteGraphNodeForInstr(&MBB[i], node);
+      noteGraphNodeForInstr(I, node);
       
       // Remember all register references and value defs
       findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
@@ -632,8 +637,8 @@
   this->addCallDepEdges(callDepNodeVec, target);
   
   // Then add incoming def-use (SSA) edges for each machine instruction.
-  for (unsigned i=0, N=MBB.size(); i < N; i++)
-    addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
+  for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
+    addEdgesForInstruction(*I, valueToDefVecMap, target);
 
   // Then add edges for dependences on machine registers
   this->addMachineRegEdges(regToRefVecMap, target);