[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterInfo.cpp X86InstrInfo.td
Alkis Evlogimenos
alkis at niobe.cs.uiuc.edu
Tue Feb 17 09:49:01 PST 2004
Changes in directory llvm/lib/Target/X86:
X86RegisterInfo.cpp updated: 1.61 -> 1.62
X86InstrInfo.td updated: 1.35 -> 1.36
---
Log message:
Add TEST and XCHG memory operand support.
---
Diffs of the changes: (+31 -1)
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.61 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.62
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.61 Tue Feb 17 09:33:14 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Tue Feb 17 09:48:42 2004
@@ -128,6 +128,9 @@
MachineInstr* NI = 0;
if (i == 0) {
switch(MI->getOpcode()) {
+ case X86::XCHGrr8: NI = MakeMRInst(X86::XCHGmr8 ,FrameIndex, MI); break;
+ case X86::XCHGrr16:NI = MakeMRInst(X86::XCHGmr16,FrameIndex, MI); break;
+ case X86::XCHGrr32:NI = MakeMRInst(X86::XCHGmr32,FrameIndex, MI); break;
case X86::MOVrr8: NI = MakeMRInst(X86::MOVmr8 , FrameIndex, MI); break;
case X86::MOVrr16: NI = MakeMRInst(X86::MOVmr16, FrameIndex, MI); break;
case X86::MOVrr32: NI = MakeMRInst(X86::MOVmr32, FrameIndex, MI); break;
@@ -187,6 +190,12 @@
case X86::XORri8: NI = MakeMIInst(X86::XORmi8 , FrameIndex, MI); break;
case X86::XORri16: NI = MakeMIInst(X86::XORmi16, FrameIndex, MI); break;
case X86::XORri32: NI = MakeMIInst(X86::XORmi32, FrameIndex, MI); break;
+ case X86::TESTrr8: NI = MakeMRInst(X86::TESTmr8 , FrameIndex, MI); break;
+ case X86::TESTrr16:NI = MakeMRInst(X86::TESTmr16, FrameIndex, MI); break;
+ case X86::TESTrr32:NI = MakeMRInst(X86::TESTmr32, FrameIndex, MI); break;
+ case X86::TESTri8: NI = MakeMIInst(X86::TESTmi8 , FrameIndex, MI); break;
+ case X86::TESTri16:NI = MakeMIInst(X86::TESTmi16, FrameIndex, MI); break;
+ case X86::TESTri32:NI = MakeMIInst(X86::TESTmi32, FrameIndex, MI); break;
case X86::CMPrr8: NI = MakeMRInst(X86::CMPmr8 , FrameIndex, MI); break;
case X86::CMPrr16: NI = MakeMRInst(X86::CMPmr16, FrameIndex, MI); break;
case X86::CMPrr32: NI = MakeMRInst(X86::CMPmr32, FrameIndex, MI); break;
@@ -197,6 +206,9 @@
}
} else if (i == 1) {
switch(MI->getOpcode()) {
+ case X86::XCHGrr8: NI = MakeRMInst(X86::XCHGrm8 ,FrameIndex, MI); break;
+ case X86::XCHGrr16:NI = MakeRMInst(X86::XCHGrm16,FrameIndex, MI); break;
+ case X86::XCHGrr32:NI = MakeRMInst(X86::XCHGrm32,FrameIndex, MI); break;
case X86::MOVrr8: NI = MakeRMInst(X86::MOVrm8 , FrameIndex, MI); break;
case X86::MOVrr16: NI = MakeRMInst(X86::MOVrm16, FrameIndex, MI); break;
case X86::MOVrr32: NI = MakeRMInst(X86::MOVrm32, FrameIndex, MI); break;
@@ -217,6 +229,9 @@
case X86::XORrr8: NI = MakeRMInst(X86::XORrm8 , FrameIndex, MI); break;
case X86::XORrr16: NI = MakeRMInst(X86::XORrm16, FrameIndex, MI); break;
case X86::XORrr32: NI = MakeRMInst(X86::XORrm32, FrameIndex, MI); break;
+ case X86::TESTrr8: NI = MakeRMInst(X86::TESTrm8 , FrameIndex, MI); break;
+ case X86::TESTrr16:NI = MakeRMInst(X86::TESTrm16, FrameIndex, MI); break;
+ case X86::TESTrr32:NI = MakeRMInst(X86::TESTrm32, FrameIndex, MI); break;
case X86::IMULrr16:NI = MakeRMInst(X86::IMULrm16, FrameIndex, MI); break;
case X86::IMULrr32:NI = MakeRMInst(X86::IMULrm32, FrameIndex, MI); break;
case X86::IMULrri16: NI = MakeRMIInst(X86::IMULrmi16, FrameIndex, MI);break;
@@ -224,7 +239,6 @@
case X86::CMPrr8: NI = MakeRMInst(X86::CMPrm8 , FrameIndex, MI); break;
case X86::CMPrr16: NI = MakeRMInst(X86::CMPrm16, FrameIndex, MI); break;
case X86::CMPrr32: NI = MakeRMInst(X86::CMPrm32, FrameIndex, MI); break;
-
case X86::MOVSXr16r8: NI = MakeRMInst(X86::MOVSXr16m8 , FrameIndex, MI); break;
case X86::MOVSXr32r8: NI = MakeRMInst(X86::MOVSXr32m8, FrameIndex, MI); break;
case X86::MOVSXr32r16:NI = MakeRMInst(X86::MOVSXr32m16, FrameIndex, MI); break;
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.35 llvm/lib/Target/X86/X86InstrInfo.td:1.36
--- llvm/lib/Target/X86/X86InstrInfo.td:1.35 Tue Feb 17 09:33:14 2004
+++ llvm/lib/Target/X86/X86InstrInfo.td Tue Feb 17 09:48:42 2004
@@ -170,6 +170,12 @@
def XCHGrr8 : X86Inst<"xchg", 0x86, MRMDestReg, Arg8>; // xchg R8, R8
def XCHGrr16 : X86Inst<"xchg", 0x87, MRMDestReg, Arg16>, OpSize;// xchg R16, R16
def XCHGrr32 : X86Inst<"xchg", 0x87, MRMDestReg, Arg32>; // xchg R32, R32
+def XCHGmr8 : X86Inst<"xchg", 0x86, MRMDestMem, Arg8>; // xchg [mem8], R8
+def XCHGmr16 : X86Inst<"xchg", 0x87, MRMDestMem, Arg16>, OpSize;// xchg [mem16], R16
+def XCHGmr32 : X86Inst<"xchg", 0x87, MRMDestMem, Arg32>; // xchg [mem32], R32
+def XCHGrm8 : X86Inst<"xchg", 0x86, MRMSrcMem , Arg8>; // xchg R8, [mem8]
+def XCHGrm16 : X86Inst<"xchg", 0x87, MRMSrcMem , Arg16>, OpSize;// xchg R16, [mem16]
+def XCHGrm32 : X86Inst<"xchg", 0x87, MRMSrcMem , Arg32>; // xchg R32, [mem32]
def LEAr16 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg16>, OpSize; // R16 = lea [mem]
def LEAr32 : X86Inst<"lea", 0x8D, MRMSrcMem, Arg32>; // R32 = lea [mem]
@@ -429,9 +435,19 @@
def TESTrr8 : X86Inst<"test", 0x84, MRMDestReg, Arg8 >; // flags = R8 & R8
def TESTrr16 : X86Inst<"test", 0x85, MRMDestReg, Arg16>, OpSize; // flags = R16 & R16
def TESTrr32 : X86Inst<"test", 0x85, MRMDestReg, Arg32>; // flags = R32 & R32
+def TESTmr8 : X86Inst<"test", 0x84, MRMDestMem, Arg8 >; // flags = [mem8] & R8
+def TESTmr16 : X86Inst<"test", 0x85, MRMDestMem, Arg16>, OpSize; // flags = [mem16] & R16
+def TESTmr32 : X86Inst<"test", 0x85, MRMDestMem, Arg32>; // flags = [mem32] & R32
+def TESTrm8 : X86Inst<"test", 0x84, MRMSrcMem , Arg8 >; // flags = R8 & [mem8]
+def TESTrm16 : X86Inst<"test", 0x85, MRMSrcMem , Arg16>, OpSize; // flags = R16 & [mem16]
+def TESTrm32 : X86Inst<"test", 0x85, MRMSrcMem , Arg32>; // flags = R32 & [mem32]
+
def TESTri8 : X86Inst<"test", 0xF6, MRMS0r , Arg8 >; // flags = R8 & imm8
def TESTri16 : X86Inst<"test", 0xF7, MRMS0r , Arg16>, OpSize; // flags = R16 & imm16
def TESTri32 : X86Inst<"test", 0xF7, MRMS0r , Arg32>; // flags = R32 & imm32
+def TESTmi8 : X86Inst<"test", 0xF6, MRMS0m , Arg8 >; // flags = [mem8] & imm8
+def TESTmi16 : X86Inst<"test", 0xF7, MRMS0m , Arg16>, OpSize; // flags = [mem16] & imm16
+def TESTmi32 : X86Inst<"test", 0xF7, MRMS0m , Arg32>; // flags = [mem32] & imm32
// Shift instructions
class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
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