[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp PeepholeOptimizer.cpp Printer.cpp X86InstrInfo.td
Chris Lattner
lattner at cs.uiuc.edu
Mon Feb 16 22:27:01 PST 2004
Changes in directory llvm/lib/Target/X86:
InstSelectSimple.cpp updated: 1.160 -> 1.161
PeepholeOptimizer.cpp updated: 1.16 -> 1.17
Printer.cpp updated: 1.82 -> 1.83
X86InstrInfo.td updated: 1.25 -> 1.26
---
Log message:
Rename the IMULri* instructions to IMULrri, as they are actually three address
instructions. Add forms of these instructions that read from memory
---
Diffs of the changes: (+44 -11)
Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.160 llvm/lib/Target/X86/InstSelectSimple.cpp:1.161
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.160 Sat Feb 14 19:04:03 2004
+++ llvm/lib/Target/X86/InstSelectSimple.cpp Mon Feb 16 22:26:43 2004
@@ -1524,10 +1524,10 @@
}
if (Class == cShort) {
- BMI(MBB, IP, X86::IMULri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+ BMI(MBB, IP, X86::IMULrri16, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
return;
} else if (Class == cInt) {
- BMI(MBB, IP, X86::IMULri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
+ BMI(MBB, IP, X86::IMULrri32, 2, DestReg).addReg(op0Reg).addZImm(ConstRHS);
return;
}
Index: llvm/lib/Target/X86/PeepholeOptimizer.cpp
diff -u llvm/lib/Target/X86/PeepholeOptimizer.cpp:1.16 llvm/lib/Target/X86/PeepholeOptimizer.cpp:1.17
--- llvm/lib/Target/X86/PeepholeOptimizer.cpp:1.16 Mon Feb 16 17:50:18 2004
+++ llvm/lib/Target/X86/PeepholeOptimizer.cpp Mon Feb 16 22:26:43 2004
@@ -72,7 +72,7 @@
// immediate despite the fact that the operands are 16 or 32 bits. Because
// this can save three bytes of code size (and icache space), we want to
// shrink them if possible.
- case X86::IMULri16: case X86::IMULri32:
+ case X86::IMULrri16: case X86::IMULrri32:
assert(MI->getNumOperands() == 3 && "These should all have 3 operands!");
if (MI->getOperand(2).isImmediate()) {
int Val = MI->getOperand(2).getImmedValue();
@@ -81,13 +81,38 @@
unsigned Opcode;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown opcode value!");
- case X86::IMULri16: Opcode = X86::IMULri16b; break;
- case X86::IMULri32: Opcode = X86::IMULri32b; break;
+ case X86::IMULrri16: Opcode = X86::IMULrri16b; break;
+ case X86::IMULrri32: Opcode = X86::IMULrri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
I = MBB.insert(MBB.erase(I),
BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
+ return true;
+ }
+ }
+ return false;
+
+ case X86::IMULrmi16: case X86::IMULrmi32:
+ assert(MI->getNumOperands() == 6 && "These should all have 6 operands!");
+ if (MI->getOperand(5).isImmediate()) {
+ int Val = MI->getOperand(5).getImmedValue();
+ // If the value is the same when signed extended from 8 bits...
+ if (Val == (signed int)(signed char)Val) {
+ unsigned Opcode;
+ switch (MI->getOpcode()) {
+ default: assert(0 && "Unknown opcode value!");
+ case X86::IMULrmi16: Opcode = X86::IMULrmi16b; break;
+ case X86::IMULrmi32: Opcode = X86::IMULrmi32b; break;
+ }
+ unsigned R0 = MI->getOperand(0).getReg();
+ unsigned R1 = MI->getOperand(1).getReg();
+ unsigned Scale = MI->getOperand(2).getImmedValue();
+ unsigned R2 = MI->getOperand(3).getReg();
+ unsigned Offset = MI->getOperand(3).getImmedValue();
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 2, R0).addReg(R1).addZImm(Scale).
+ addReg(R2).addSImm(Offset).addZImm((char)Val));
return true;
}
}
Index: llvm/lib/Target/X86/Printer.cpp
diff -u llvm/lib/Target/X86/Printer.cpp:1.82 llvm/lib/Target/X86/Printer.cpp:1.83
--- llvm/lib/Target/X86/Printer.cpp:1.82 Sun Feb 15 15:37:17 2004
+++ llvm/lib/Target/X86/Printer.cpp Mon Feb 16 22:26:43 2004
@@ -665,7 +665,7 @@
// like: add r32, r/m32
//
// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
- // for instructions like the IMULri instructions.
+ // for instructions like the IMULrri instructions.
//
//
assert(MI->getOperand(0).isRegister() &&
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.25 llvm/lib/Target/X86/X86InstrInfo.td:1.26
--- llvm/lib/Target/X86/X86InstrInfo.td:1.25 Mon Feb 16 17:48:42 2004
+++ llvm/lib/Target/X86/X86InstrInfo.td Mon Feb 16 22:26:43 2004
@@ -299,12 +299,20 @@
def IMULrr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
def IMULrr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
+def IMULrm16 : I2A16<"imul", 0xAF, MRMSrcMem>, TB, OpSize;
+def IMULrm32 : I2A32<"imul", 0xAF, MRMSrcMem>, TB ;
+
+
+// These are suprisingly enough not two address instructions!
+def IMULrri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize; // R16 = R16*I16
+def IMULrri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>; // R32 = R32*I32
+def IMULrri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >, OpSize; // R16 = R16*I8
+def IMULrri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8 >; // R32 = R32*I8
+def IMULrmi16 : X86Inst<"imul", 0x69, MRMSrcMem, Arg16>, OpSize; // R16 = [mem16]*I16
+def IMULrmi32 : X86Inst<"imul", 0x69, MRMSrcMem, Arg32>; // R32 = [mem32]*I32
+def IMULrmi16b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >, OpSize; // R16 = [mem16]*I8
+def IMULrmi32b : X86Inst<"imul", 0x6B, MRMSrcMem, Arg8 >; // R32 = [mem32]*I8
-// These are suprisingly enough not two addres instructions!
-def IMULri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize;
-def IMULri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>;
-def IMULri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>, OpSize;
-def IMULri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>;
// Logical operators...
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