[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp X86RegisterInfo.h X86RegisterInfo.cpp X86CodeEmitter.cpp Printer.cpp PeepholeOptimizer.cpp InstSelectSimple.cpp FloatingPoint.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Wed Feb 11 20:28:09 PST 2004
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.46 -> 1.47
X86RegisterInfo.h updated: 1.18 -> 1.19
X86RegisterInfo.cpp updated: 1.41 -> 1.42
X86CodeEmitter.cpp updated: 1.47 -> 1.48
Printer.cpp updated: 1.79 -> 1.80
PeepholeOptimizer.cpp updated: 1.12 -> 1.13
InstSelectSimple.cpp updated: 1.154 -> 1.155
FloatingPoint.cpp updated: 1.20 -> 1.21
---
Log message:
Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
---
Diffs of the changes: (+86 -86)
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.46 llvm/lib/Target/X86/X86TargetMachine.cpp:1.47
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.46 Sun Feb 8 19:47:10 2004
+++ llvm/lib/Target/X86/X86TargetMachine.cpp Wed Feb 11 20:27:09 2004
@@ -104,9 +104,6 @@
if (!DisableOutput)
PM.add(createX86CodePrinterPass(Out, *this));
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
-
return false; // success!
}
Index: llvm/lib/Target/X86/X86RegisterInfo.h
diff -u llvm/lib/Target/X86/X86RegisterInfo.h:1.18 llvm/lib/Target/X86/X86RegisterInfo.h:1.19
--- llvm/lib/Target/X86/X86RegisterInfo.h:1.18 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/X86/X86RegisterInfo.h Wed Feb 11 20:27:09 2004
@@ -28,25 +28,26 @@
/// Code Generation virtual methods...
int storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const;
int loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const;
- int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
+ int copyRegToReg(MachineBasicBlock &MBB,
+ MachineInstr* MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
int eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const;
+ MachineInstr* MI) const;
int eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const;
+ MachineInstr* MI) const;
int processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.41 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.42
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.41 Wed Feb 4 16:17:40 2004
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Feb 11 20:27:09 2004
@@ -47,37 +47,35 @@
}
int X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned SrcReg, int FrameIdx,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] =
{ X86::MOVrm8, X86::MOVrm16, X86::MOVrm32, X86::FSTPr80 };
- MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
+ MachineInstr *I = addFrameReference(BuildMI(Opcode[getIdx(RC)], 5),
FrameIdx).addReg(SrcReg);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MI, I);
return 1;
}
int X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const{
static const unsigned Opcode[] =
{ X86::MOVmr8, X86::MOVmr16, X86::MOVmr32, X86::FLDr80 };
- MachineInstr *MI = addFrameReference(BuildMI(Opcode[getIdx(RC)], 4, DestReg),
- FrameIdx);
- MBBI = MBB.insert(MBBI, MI)+1;
+ unsigned OC = Opcode[getIdx(RC)];
+ MBB.insert(MI, addFrameReference(BuildMI(OC, 4, DestReg), FrameIdx));
return 1;
}
int X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineInstr* MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const {
static const unsigned Opcode[] =
{ X86::MOVrr8, X86::MOVrr16, X86::MOVrr32, X86::FpMOV };
- MachineInstr *MI = BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MI, BuildMI(Opcode[getIdx(RC)],1,DestReg).addReg(SrcReg));
return 1;
}
@@ -95,8 +93,8 @@
int X86RegisterInfo::eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const {
- MachineInstr *New = 0, *Old = *I;;
+ MachineInstr* I) const {
+ MachineInstr *New = 0, *Old = I;
if (hasFP(MF)) {
// If we have a frame pointer, turn the adjcallstackup instruction into a
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
@@ -119,20 +117,19 @@
}
if (New) {
- *I = New; // Replace the pseudo instruction with a new instruction...
- delete Old;
+ // Replace the pseudo instruction with a new instruction...
+ MBB.insert(MBB.erase(I), New);
return 0;
} else {
- I = MBB.erase(I);// Just delete the pseudo instruction...
- delete Old;
+ MBB.erase(I);
return -1;
}
}
int X86RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const {
+ MachineInstr* II) const {
unsigned i = 0;
- MachineInstr &MI = **II;
+ MachineInstr &MI = *II;
while (!MI.getOperand(i).isFrameIndex()) {
++i;
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
@@ -182,13 +179,13 @@
if (NumBytes) { // adjust stack pointer: ESP -= numbytes
MI= BuildMI(X86::SUBri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MBBI, MI);
}
// Save EBP into the appropriate stack slot...
MI = addRegOffset(BuildMI(X86::MOVrm32, 5), // mov [ESP-<offset>], EBP
X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MBBI, MI);
// Update EBP with the new base value...
if (NumBytes == 0) // mov EBP, ESP
@@ -196,7 +193,7 @@
else // lea EBP, [ESP+StackSize]
MI = addRegOffset(BuildMI(X86::LEAr32, 5, X86::EBP), X86::ESP, NumBytes);
- MBBI = MBB.insert(MBBI, MI)+1;
+ MBB.insert(MBBI, MI);
} else {
// When we have no frame pointer, we reserve argument space for call sites
@@ -226,9 +223,9 @@
MachineBasicBlock &MBB) const {
unsigned oldSize = MBB.size();
const MachineFrameInfo *MFI = MF.getFrameInfo();
- MachineBasicBlock::iterator MBBI = MBB.end()-1;
+ MachineBasicBlock::iterator MBBI = MBB.end(); --MBBI;
MachineInstr *MI;
- assert((*MBBI)->getOpcode() == X86::RET &&
+ assert(MBBI->getOpcode() == X86::RET &&
"Can only insert epilog into returning blocks");
if (hasFP(MF)) {
@@ -238,18 +235,18 @@
// mov ESP, EBP
MI = BuildMI(X86::MOVrr32, 1,X86::ESP).addReg(X86::EBP);
- MBBI = 1+MBB.insert(MBBI, MI);
+ MBB.insert(MBBI, MI);
// mov EBP, [ESP-<offset>]
MI = addRegOffset(BuildMI(X86::MOVmr32, 5, X86::EBP), X86::ESP, EBPOffset);
- MBBI = 1+MBB.insert(MBBI, MI);
+ MBB.insert(MBBI, MI);
} else {
// Get the number of bytes allocated from the FrameInfo...
unsigned NumBytes = MFI->getStackSize();
if (NumBytes) { // adjust stack pointer back: ESP += numbytes
MI =BuildMI(X86::ADDri32, 1, X86::ESP, MOTy::UseAndDef).addZImm(NumBytes);
- MBBI = 1+MBB.insert(MBBI, MI);
+ MBB.insert(MBBI, MI);
}
}
return MBB.size() - oldSize;
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.47 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.48
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.47 Wed Feb 4 16:17:40 2004
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Wed Feb 11 20:27:09 2004
@@ -212,8 +212,6 @@
bool X86TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
MachineCodeEmitter &MCE) {
PM.add(new Emitter(MCE));
- // Delete machine code for this function
- PM.add(createMachineCodeDeleter());
return false;
}
@@ -242,7 +240,7 @@
BasicBlockAddrs[MBB.getBasicBlock()] = Addr;
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
- emitInstruction(**I);
+ emitInstruction(*I);
}
Index: llvm/lib/Target/X86/Printer.cpp
diff -u llvm/lib/Target/X86/Printer.cpp:1.79 llvm/lib/Target/X86/Printer.cpp:1.80
--- llvm/lib/Target/X86/Printer.cpp:1.79 Wed Feb 11 13:26:28 2004
+++ llvm/lib/Target/X86/Printer.cpp Wed Feb 11 20:27:09 2004
@@ -365,7 +365,7 @@
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- printMachineInstruction(*II);
+ printMachineInstruction(II);
}
}
Index: llvm/lib/Target/X86/PeepholeOptimizer.cpp
diff -u llvm/lib/Target/X86/PeepholeOptimizer.cpp:1.12 llvm/lib/Target/X86/PeepholeOptimizer.cpp:1.13
--- llvm/lib/Target/X86/PeepholeOptimizer.cpp:1.12 Tue Feb 10 15:18:45 2004
+++ llvm/lib/Target/X86/PeepholeOptimizer.cpp Wed Feb 11 20:27:09 2004
@@ -50,8 +50,11 @@
bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
- MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
+ assert(I != MBB.end());
+ MachineBasicBlock::iterator NextI = I; ++NextI;
+
+ MachineInstr *MI = I;
+ MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
unsigned Size = 0;
switch (MI->getOpcode()) {
case X86::MOVrr8:
@@ -59,7 +62,6 @@
case X86::MOVrr32: // Destroy X = X copies...
if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
I = MBB.erase(I);
- delete MI;
return true;
}
return false;
@@ -82,8 +84,8 @@
}
unsigned R0 = MI->getOperand(0).getReg();
unsigned R1 = MI->getOperand(1).getReg();
- *I = BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 2, R0).addReg(R1).addZImm((char)Val));
return true;
}
}
@@ -114,8 +116,8 @@
case X86::XORri32: Opcode = X86::XORri32b; break;
}
unsigned R0 = MI->getOperand(0).getReg();
- *I = BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode, 1, R0, MOTy::UseAndDef).addZImm((char)Val));
return true;
}
}
@@ -132,8 +134,8 @@
if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
static const unsigned Opcode[] ={X86::XORrr8,X86::XORrr16,X86::XORrr32};
unsigned Reg = MI->getOperand(0).getReg();
- *I = BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg);
- delete MI;
+ I = MBB.insert(MBB.erase(I),
+ BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
return true;
} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
// TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
@@ -145,8 +147,6 @@
if (Next->getOpcode() == X86::BSWAPr32 &&
MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
I = MBB.erase(MBB.erase(I));
- delete MI;
- delete Next;
return true;
}
return false;
@@ -189,12 +189,11 @@
virtual bool runOnMachineFunction(MachineFunction &MF) {
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI!=E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); ++I) {
- MachineInstr *MI = *I;
- for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- MachineOperand &MO = MI->getOperand(i);
+ for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
+ MachineOperand &MO = I->getOperand(i);
if (MO.isRegister() && MO.isDef() && !MO.isUse() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
- setDefinition(MO.getReg(), MI);
+ setDefinition(MO.getReg(), I);
}
}
return false;
@@ -377,8 +376,10 @@
bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
- MachineInstr *Next = (I+1 != MBB.end()) ? *(I+1) : 0;
+ MachineBasicBlock::iterator NextI = I; ++NextI;
+
+ MachineInstr *MI = I;
+ MachineInstr *Next = (NextI != MBB.end()) ? &*NextI : (MachineInstr*)0;
bool Changed = false;
Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.154 llvm/lib/Target/X86/InstSelectSimple.cpp:1.155
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.154 Sun Feb 8 22:37:30 2004
+++ llvm/lib/Target/X86/InstSelectSimple.cpp Wed Feb 11 20:27:09 2004
@@ -37,23 +37,21 @@
/// instruction at as well as a basic block. This is the version for when you
/// have a destination register in mind.
inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands,
unsigned DestReg) {
- assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1, true, true);
- I = MBB->insert(I, MI)+1;
+ MBB->insert(I, MI);
return MachineInstrBuilder(MI).addReg(DestReg, MOTy::Def);
}
/// BMI - A special BuildMI variant that takes an iterator to insert the
/// instruction at as well as a basic block.
inline static MachineInstrBuilder BMI(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator &I,
+ MachineBasicBlock::iterator I,
int Opcode, unsigned NumOperands) {
- assert(I >= MBB->begin() && I <= MBB->end() && "Bad iterator!");
MachineInstr *MI = new MachineInstr(Opcode, NumOperands, true, true);
- I = MBB->insert(I, MI)+1;
+ MBB->insert(I, MI);
return MachineInstrBuilder(MI);
}
@@ -541,19 +539,19 @@
MachineBasicBlock *MBB = MBBMap[I];
// Loop over all of the PHI nodes in the LLVM basic block...
- unsigned NumPHIs = 0;
+ MachineInstr* instr = MBB->begin();
for (BasicBlock::const_iterator I = BB->begin();
PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
// Create a new machine instr PHI node, and insert it.
unsigned PHIReg = getReg(*PN);
MachineInstr *PhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg);
- MBB->insert(MBB->begin()+NumPHIs++, PhiMI);
+ MBB->insert(instr, PhiMI);
MachineInstr *LongPhiMI = 0;
if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy) {
LongPhiMI = BuildMI(X86::PHI, PN->getNumOperands(), PHIReg+1);
- MBB->insert(MBB->begin()+NumPHIs++, LongPhiMI);
+ MBB->insert(instr, LongPhiMI);
}
// PHIValues - Map of blocks to incoming virtual registers. We use this
@@ -588,7 +586,7 @@
MachineBasicBlock::iterator PI = PredMBB->begin();
// Skip over any PHI nodes though!
- while (PI != PredMBB->end() && (*PI)->getOpcode() == X86::PHI)
+ while (PI != PredMBB->end() && PI->getOpcode() == X86::PHI)
++PI;
ValReg = getReg(Val, PredMBB, PI);
Index: llvm/lib/Target/X86/FloatingPoint.cpp
diff -u llvm/lib/Target/X86/FloatingPoint.cpp:1.20 llvm/lib/Target/X86/FloatingPoint.cpp:1.21
--- llvm/lib/Target/X86/FloatingPoint.cpp:1.20 Tue Feb 10 14:31:28 2004
+++ llvm/lib/Target/X86/FloatingPoint.cpp Wed Feb 11 20:27:09 2004
@@ -118,7 +118,7 @@
// Emit an fxch to update the runtime processors version of the state
MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
- I = 1+MBB->insert(I, MI);
+ MBB->insert(I, MI);
NumFXCH++;
}
}
@@ -129,7 +129,7 @@
pushReg(AsReg); // New register on top of stack
MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
- I = 1+MBB->insert(I, MI);
+ MBB->insert(I, MI);
}
// popStackAfter - Pop the current value off of the top of the FP stack
@@ -193,12 +193,17 @@
MBB = &BB;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
- MachineInstr *PrevMI = I == BB.begin() ? 0 : *(I-1);
+ MachineInstr *PrevMI = 0;
+ if (I != BB.begin()) {
+ MachineBasicBlock::iterator tmp = I;
+ --tmp;
+ PrevMI = tmp;
+ }
++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t";
@@ -242,15 +247,17 @@
}
// Print out all of the instructions expanded to if -debug
- DEBUG(if (*I == PrevMI) {
+ DEBUG(if (&*I == PrevMI) {
std::cerr<< "Just deleted pseudo instruction\n";
} else {
MachineBasicBlock::iterator Start = I;
// Rewind to first instruction newly inserted.
- while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
+ while (Start != BB.begin() &&
+ --Start != MachineBasicBlock::iterator(PrevMI));
+ ++Start;
std::cerr << "Inserted instructions:\n\t";
- (*Start)->print(std::cerr, MF.getTarget());
- while (++Start != I+1);
+ Start->print(std::cerr, MF.getTarget());
+ while (++Start != I); ++Start;
}
dumpStack();
);
@@ -344,15 +351,15 @@
RegMap[Stack[--StackTop]] = ~0; // Update state
// Check to see if there is a popping version of this instruction...
- int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), (*I)->getOpcode());
+ int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), I->getOpcode());
if (Opcode != -1) {
- (*I)->setOpcode(Opcode);
+ I->setOpcode(Opcode);
if (Opcode == X86::FUCOMPPr)
- (*I)->RemoveOperand(0);
+ I->RemoveOperand(0);
} else { // Insert an explicit pop
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
- I = MBB->insert(I+1, MI);
+ I = MBB->insert(++I, MI);
}
}
@@ -371,7 +378,7 @@
/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
///
void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned DestReg = getFPReg(MI->getOperand(0));
MI->RemoveOperand(0); // Remove the explicit ST(0) operand
@@ -382,7 +389,7 @@
/// handleOneArgFP - fst <mem>, ST(0)
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
assert((MI->getNumOperands() == 5 || MI->getNumOperands() == 1) &&
"Can only handle fst* & ftst instructions!");
@@ -418,7 +425,7 @@
/// handleOneArgFPRW - fchs - ST(0) = -ST(0)
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
assert(MI->getNumOperands() == 2 && "Can only handle fst* instructions!");
// Is this the last use of the source register?
@@ -503,7 +510,7 @@
void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
unsigned NumOperands = MI->getNumOperands();
assert(NumOperands == 3 ||
@@ -588,7 +595,8 @@
unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
// Replace the old instruction with a new instruction
- *I = BuildMI(Opcode, 1).addReg(getSTReg(NotTOS));
+ MBB->remove(I);
+ I = MBB->insert(I, BuildMI(Opcode, 1).addReg(getSTReg(NotTOS)));
// If both operands are killed, pop one off of the stack in addition to
// overwriting the other one.
@@ -617,7 +625,7 @@
Stack[--StackTop] = ~0;
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
- I = MBB->insert(I+1, MI);
+ I = MBB->insert(++I, MI);
}
}
}
@@ -639,7 +647,7 @@
/// instructions.
///
void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
- MachineInstr *MI = *I;
+ MachineInstr *MI = I;
switch (MI->getOpcode()) {
default: assert(0 && "Unknown SpecialFP instruction!");
case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
@@ -675,6 +683,6 @@
}
}
- I = MBB->erase(I)-1; // Remove the pseudo instruction
- delete MI;
+ I = MBB->erase(I); // Remove the pseudo instruction
+ --I;
}
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