[llvm-commits] CVS: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen:

TwoAddressInstructionPass.cpp updated: 1.8 -> 1.9

---
Log message:

Fix, correctly this time, the computation of the return value
Fix a spello
Tighten up the assertion checking

No functionality changes.



---
Diffs of the changes:  (+16 -15)

Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.8 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.9
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.8	Sat Jan 31 15:14:04 2004
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp	Sat Jan 31 15:21:43 2004
@@ -73,8 +73,8 @@
     DEBUG(std::cerr << "Machine Function\n");
     const TargetMachine &TM = MF.getTarget();
     const MRegisterInfo &MRI = *TM.getRegisterInfo();
-    LiveVariables &LV = getAnalysis<LiveVariables>();
     const TargetInstrInfo &TII = TM.getInstrInfo();
+    LiveVariables &LV = getAnalysis<LiveVariables>();
 
     bool MadeChange = false;
 
@@ -90,19 +90,20 @@
                 continue;
 
             ++numTwoAddressInstrs;
-            MadeChange = true;
 
             DEBUG(std::cerr << "\tinstruction: "; mi->print(std::cerr, TM));
 
+            assert(mi->getOperand(1).isRegister() &&
+                   mi->getOperand(1).getAllocatedRegNum() &&
+                   mi->getOperand(1).isUse() &&
+                   "two address instruction invalid");
+
             // we have nothing to do if the two operands are the same
             if (mi->getOperand(0).getAllocatedRegNum() ==
                 mi->getOperand(1).getAllocatedRegNum())
                 continue;
 
-            assert(mi->getOperand(1).isRegister() &&
-                   mi->getOperand(1).getAllocatedRegNum() &&
-                   mi->getOperand(1).isUse() &&
-                   "two address instruction invalid");
+            MadeChange = true;
 
             // rewrite:
             //     a = b op c
@@ -112,28 +113,28 @@
             unsigned regA = mi->getOperand(0).getAllocatedRegNum();
             unsigned regB = mi->getOperand(1).getAllocatedRegNum();
 
-            assert(regA >= MRegisterInfo::FirstVirtualRegister &&
-                   regB >= MRegisterInfo::FirstVirtualRegister &&
+            assert(MRegisterInfo::isVirtualRegister(regA) &&
+                   MRegisterInfo::isVirtualRegister(regB) &&
                    "cannot update physical register live information");
 
             // first make sure we do not have a use of a in the
             // instruction (a = b + a for example) because our
-            // transofrmation will not work. This should never occur
-            // because of SSA.
-            for (unsigned i = 1; i < mi->getNumOperands(); ++i) {
+            // transformation will not work. This should never occur
+            // because we are in SSA form.
+            for (unsigned i = 1; i != mi->getNumOperands(); ++i)
                 assert(!mi->getOperand(i).isRegister() ||
                        mi->getOperand(i).getAllocatedRegNum() != (int)regA);
-            }
 
-            const TargetRegisterClass* rc =
-                MF.getSSARegMap()->getRegClass(regA);
-            numInstrsAdded += MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
+            const TargetRegisterClass* rc =MF.getSSARegMap()->getRegClass(regA);
+            unsigned Added = MRI.copyRegToReg(*mbbi, mii, regA, regB, rc);
+            numInstrsAdded += Added;
 
             MachineInstr* prevMi = *(mii - 1);
             DEBUG(std::cerr << "\t\tadded instruction: ";
                   prevMi->print(std::cerr, TM));
 
             // update live variables for regA
+            assert(Added == 1 && "Cannot handle multi-instruction copies yet!");
             LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
             varInfo.DefInst = prevMi;