[llvm-commits] CVS: llvm/utils/TableGen/InstrSelectorEmitter.cpp

[Brian Gaeke]

Changes in directory llvm/utils/TableGen:

InstrSelectorEmitter.cpp updated: 1.37 -> 1.38

---
Log message:

Fix a couple of places I noticed where "X86" was hard-coded.

---
Diffs of the changes:  (+2 -2)

Index: llvm/utils/TableGen/InstrSelectorEmitter.cpp
diff -u llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.37 llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.38
--- llvm/utils/TableGen/InstrSelectorEmitter.cpp:1.37	Wed Dec 10 18:58:34 2003
+++ llvm/utils/TableGen/InstrSelectorEmitter.cpp	Sat Jan 24 03:23:46 2004
@@ -1023,7 +1023,7 @@
      << "  class " << Target.getName() << "ISel {\n"
      << "    SelectionDAG &DAG;\n"
      << "  public:\n"
-     << "    X86ISel(SelectionDAG &D) : DAG(D) {}\n"
+     << "    " << Target.getName () << "ISel(SelectionDAG &D) : DAG(D) {}\n"
      << "    void generateCode();\n"
      << "  private:\n"
      << "    unsigned makeAnotherReg(const TargetRegisterClass *RC) {\n"
@@ -1060,7 +1060,7 @@
   OS << "  };\n}\n\n";
 
   // Emit the generateCode entry-point...
-  OS << "void X86ISel::generateCode() {\n"
+  OS << "void " << Target.getName () << "ISel::generateCode() {\n"
      << "  SelectionDAGNode *Root = DAG.getRoot();\n"
      << "  assert(Root->getValueType() == MVT::isVoid && "
                                        "\"Root of DAG produces value??\");\n\n"