[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.h X86InstrInfo.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Sun Dec 28 11:36:05 PST 2003
Changes in directory llvm/lib/Target/X86:
X86InstrInfo.h updated: 1.29 -> 1.30
X86InstrInfo.cpp updated: 1.17 -> 1.18
---
Log message:
Add TargetInstrInfo::isMoveInstr() to support coalescing in register
allocation.
---
Diffs of the changes: (+23 -0)
Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.29 llvm/lib/Target/X86/X86InstrInfo.h:1.30
--- llvm/lib/Target/X86/X86InstrInfo.h:1.29 Fri Dec 19 19:22:04 2003
+++ llvm/lib/Target/X86/X86InstrInfo.h Sun Dec 28 11:35:07 2003
@@ -169,6 +169,14 @@
///
MachineInstr* createNOPinstr() const;
+ //
+ // Return true if the instruction is a register to register move and
+ // leave the source and dest operands in the passed parameters.
+ //
+ virtual bool isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const;
+
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
/// more than one way to `do nothing' but only one canonical way to slack off.
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.17 llvm/lib/Target/X86/X86InstrInfo.cpp:1.18
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.17 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/X86/X86InstrInfo.cpp Sun Dec 28 11:35:07 2003
@@ -51,3 +51,18 @@
return false;
}
+bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
+ unsigned& sourceReg,
+ unsigned& destReg) const {
+ MachineOpCode oc = MI.getOpcode();
+ if (oc == X86::MOVrr8 || oc == X86::MOVrr16 || oc == X86::MOVrr32) {
+ assert(MI.getNumOperands() == 2 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ "invalid register-register move instruction");
+ sourceReg = MI.getOperand(1).getAllocatedRegNum();
+ destReg = MI.getOperand(0).getAllocatedRegNum();
+ return true;
+ }
+ return false;
+}
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