[llvm-commits] CVS: llvm/lib/Target/X86/X86TargetMachine.cpp X86InstrInfo.td X86CodeEmitter.cpp InstSelectSimple.cpp FloatingPoint.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Sat Dec 20 10:24:01 PST 2003
Changes in directory llvm/lib/Target/X86:
X86TargetMachine.cpp updated: 1.41 -> 1.42
X86InstrInfo.td updated: 1.14 -> 1.15
X86CodeEmitter.cpp updated: 1.45 -> 1.46
InstSelectSimple.cpp updated: 1.142 -> 1.143
FloatingPoint.cpp updated: 1.15 -> 1.16
---
Log message:
Remove floating point killer pass. This is now implemented in the
instruction selector by adding a new pseudo-instruction
FP_REG_KILL. This instruction implicitly defines all x86 fp registers
and is a terminator so that passes which add machine code at the end
of basic blocks (like phi elimination) do not add instructions between
it and the branch or return instruction.
---
Diffs of the changes: (+8 -64)
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.41 llvm/lib/Target/X86/X86TargetMachine.cpp:1.42
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.41 Sat Dec 20 04:20:19 2003
+++ llvm/lib/Target/X86/X86TargetMachine.cpp Sat Dec 20 10:22:59 2003
@@ -76,11 +76,6 @@
if (PrintCode)
PM.add(createMachineFunctionPrinterPass());
- // kill floating point registers at the end of basic blocks. this is
- // done because the floating point register stackifier cannot handle
- // floating point regs that are live across basic blocks.
- //PM.add(createX86FloatingPointKillerPass());
-
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
@@ -137,11 +132,6 @@
// Print the instruction selected machine code...
if (PrintCode)
PM.add(createMachineFunctionPrinterPass());
-
- // kill floating point registers at the end of basic blocks. this is
- // done because the floating point register stackifier cannot handle
- // floating point regs that are live across basic blocks.
- //PM.add(createX86FloatingPointKillerPass());
// Perform register allocation to convert to a concrete x86 representation
PM.add(createRegisterAllocator());
Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.14 llvm/lib/Target/X86/X86InstrInfo.td:1.15
--- llvm/lib/Target/X86/X86InstrInfo.td:1.14 Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/X86/X86InstrInfo.td Sat Dec 20 10:22:59 2003
@@ -115,7 +115,9 @@
def ADJCALLSTACKUP : X86Inst<"ADJCALLSTACKUP", 0, Pseudo, NoArg>;
def IMPLICIT_USE : X86Inst<"IMPLICIT_USE", 0, Pseudo, NoArg>;
def IMPLICIT_DEF : X86Inst<"IMPLICIT_DEF", 0, Pseudo, NoArg>;
-
+let isTerminator = 1 in
+ let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
+ def FP_REG_KILL : X86Inst<"FP_REG_KILL", 0, Pseudo, NoArg>;
//===----------------------------------------------------------------------===//
// Control Flow Instructions...
//
Index: llvm/lib/Target/X86/X86CodeEmitter.cpp
diff -u llvm/lib/Target/X86/X86CodeEmitter.cpp:1.45 llvm/lib/Target/X86/X86CodeEmitter.cpp:1.46
--- llvm/lib/Target/X86/X86CodeEmitter.cpp:1.45 Sat Dec 20 04:20:19 2003
+++ llvm/lib/Target/X86/X86CodeEmitter.cpp Sat Dec 20 10:22:59 2003
@@ -493,7 +493,9 @@
switch (Desc.TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
case X86II::Pseudo:
- if (Opcode != X86::IMPLICIT_USE && Opcode != X86::IMPLICIT_DEF)
+ if (Opcode != X86::IMPLICIT_USE &&
+ Opcode != X86::IMPLICIT_DEF &&
+ Opcode != X86::FP_REG_KILL)
std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI;
break;
Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.142 llvm/lib/Target/X86/InstSelectSimple.cpp:1.143
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.142 Sat Nov 22 00:49:41 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp Sat Dec 20 10:22:59 2003
@@ -834,6 +834,7 @@
/// ret float/double : Top of FP stack
///
void ISel::visitReturnInst(ReturnInst &I) {
+ BuildMI(BB, X86::FP_REG_KILL, 0);
if (I.getNumOperands() == 0) {
BuildMI(BB, X86::RET, 0); // Just emit a 'ret' instruction
return;
@@ -882,6 +883,7 @@
///
void ISel::visitBranchInst(BranchInst &BI) {
BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
+ BuildMI(BB, X86::FP_REG_KILL, 0);
if (!BI.isConditional()) { // Unconditional branch?
if (BI.getSuccessor(0) != NextBB)
Index: llvm/lib/Target/X86/FloatingPoint.cpp
diff -u llvm/lib/Target/X86/FloatingPoint.cpp:1.15 llvm/lib/Target/X86/FloatingPoint.cpp:1.16
--- llvm/lib/Target/X86/FloatingPoint.cpp:1.15 Sat Dec 20 04:12:17 2003
+++ llvm/lib/Target/X86/FloatingPoint.cpp Sat Dec 20 10:22:59 2003
@@ -603,55 +603,3 @@
I = MBB->erase(I)-1; // Remove the pseudo instruction
delete MI;
}
-
-namespace {
- struct FPK : public MachineFunctionPass {
- virtual const char *getPassName() const { return "X86 FP Killer"; }
- virtual bool runOnMachineFunction(MachineFunction &MF);
- virtual void getAnalysisUsage(AnalysisUsage &AU) const {
- AU.addPreserved<LiveVariables>();
- AU.addRequired<LiveVariables>();
- AU.addPreservedID(PHIEliminationID);
- AU.addRequiredID(PHIEliminationID);
- MachineFunctionPass::getAnalysisUsage(AU);
- }
- };
-}
-
-FunctionPass *llvm::createX86FloatingPointKillerPass() { return new FPK(); }
-
-bool FPK::runOnMachineFunction(MachineFunction &MF) {
- const TargetInstrInfo& tii = MF.getTarget().getInstrInfo();;
- LiveVariables &LV = getAnalysis<LiveVariables>();
-
- for (MachineFunction::iterator
- mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) {
- MachineBasicBlock& mbb = *mbbi;
- MachineBasicBlock::reverse_iterator mii = mbb.rbegin();
- // rewind to the last non terminating instruction
- while (mii != mbb.rend() && tii.isTerminatorInstr((*mii)->getOpcode()))
- ++mii;
-
- // add implicit def for all virtual floating point registers so that
- // they are spilled at the end of each basic block, since our
- // register stackifier doesn't handle them otherwise.
- MachineInstr* instr = BuildMI(X86::IMPLICIT_DEF, 7)
- .addReg(X86::FP6, MOTy::Def)
- .addReg(X86::FP5, MOTy::Def)
- .addReg(X86::FP4, MOTy::Def)
- .addReg(X86::FP3, MOTy::Def)
- .addReg(X86::FP2, MOTy::Def)
- .addReg(X86::FP1, MOTy::Def)
- .addReg(X86::FP0, MOTy::Def);
-
- mbb.insert(mii.base(), instr);
-
- for (unsigned i = 0; i < instr->getNumOperands(); ++i) {
- LV.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), instr);
-
- // force live variables to compute that these registers are dead
- LV.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), 0);
- }
- }
- return true;
-}
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