[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp RegAllocLocal.cpp RegAllocLinearScan.cpp PrologEpilogInserter.cpp PHIElimination.cpp MachineInstr.cpp LiveVariables.cpp LiveIntervals.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Sun Dec 14 07:26:39 PST 2003
Changes in directory llvm/lib/CodeGen:
RegAllocSimple.cpp updated: 1.46 -> 1.47
RegAllocLocal.cpp updated: 1.33 -> 1.34
RegAllocLinearScan.cpp updated: 1.9 -> 1.10
PrologEpilogInserter.cpp updated: 1.15 -> 1.16
PHIElimination.cpp updated: 1.13 -> 1.14
MachineInstr.cpp updated: 1.81 -> 1.82
LiveVariables.cpp updated: 1.12 -> 1.13
LiveIntervals.cpp updated: 1.6 -> 1.7
---
Log message:
Change interface of MachineOperand as follows:
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
b) add isUse(), isDef()
c) rename opHiBits32() to isHiBits32(),
opLoBits32() to isLoBits32(),
opHiBits64() to isHiBits64(),
opLoBits64() to isLoBits64().
This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.
---
Diffs of the changes: (+53 -49)
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.46 llvm/lib/CodeGen/RegAllocSimple.cpp:1.47
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.46 Tue Nov 11 16:41:32 2003
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Sun Dec 14 07:24:16 2003
@@ -184,13 +184,13 @@
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.opIsDefOnly() || op.opIsDefAndUse()) {
+ if (op.isDef()) {
if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
MI->getOperand(1).getAllocatedRegNum() &&
- MI->getOperand(1).opIsUse() &&
+ MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
physReg = MI->getOperand(1).getAllocatedRegNum();
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.33 llvm/lib/CodeGen/RegAllocLocal.cpp:1.34
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.33 Fri Dec 12 19:20:58 2003
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Sun Dec 14 07:24:16 2003
@@ -507,7 +507,9 @@
// to be live-in, or the input is badly hosed.
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).opIsUse() && MI->getOperand(i).isVirtualRegister()){
+ if (MI->getOperand(i).isUse() &&
+ !MI->getOperand(i).isDef() &&
+ MI->getOperand(i).isVirtualRegister()){
unsigned VirtSrcReg = MI->getOperand(i).getAllocatedRegNum();
unsigned PhysSrcReg = reloadVirtReg(MBB, I, VirtSrcReg);
MI->SetMachineOperandReg(i, PhysSrcReg); // Assign the input register
@@ -541,8 +543,7 @@
// Loop over all of the operands of the instruction, spilling registers that
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if ((MI->getOperand(i).opIsDefOnly() ||
- MI->getOperand(i).opIsDefAndUse()) &&
+ if (MI->getOperand(i).isDef() &&
MI->getOperand(i).isPhysicalRegister()) {
unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
spillPhysReg(MBB, I, Reg, true); // Spill any existing value in the reg
@@ -565,8 +566,8 @@
// we need to scavenge a register.
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse())
- && MI->getOperand(i).isVirtualRegister()) {
+ if (MI->getOperand(i).isDef() &&
+ MI->getOperand(i).isVirtualRegister()) {
unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
unsigned DestPhysReg;
@@ -585,7 +586,7 @@
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isPhysicalRegister() &&
MI->getOperand(1).getAllocatedRegNum() &&
- MI->getOperand(1).opIsUse() &&
+ MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
DestPhysReg = MI->getOperand(1).getAllocatedRegNum();
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.9 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.10
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.9 Sat Dec 13 05:58:10 2003
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Sun Dec 14 07:24:16 2003
@@ -213,7 +213,7 @@
ii = mbb->begin(), ie = mbb->end();
ii != ie; ++ii) {
MachineInstr* instr = *ii;
-
+
std::cerr << i++ << "\t";
instr->print(std::cerr, *tm_);
}
@@ -245,7 +245,6 @@
DEBUG(printIntervals("\tactive", active_.begin(), active_.end()));
DEBUG(printIntervals("\tinactive", inactive_.begin(), inactive_.end()));
-
processActiveIntervals(i);
// processInactiveIntervals(i);
@@ -281,7 +280,7 @@
}
// remove interval from active
}
-
+
DEBUG(std::cerr << "finished register allocation\n");
DEBUG(printVirt2PhysMap());
@@ -322,7 +321,7 @@
for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
i != e; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister() && op.opIsUse()) {
+ if (op.isVirtualRegister() && op.isUse()) {
unsigned virtReg = op.getAllocatedRegNum();
unsigned physReg = v2pMap_[virtReg];
if (!physReg) {
@@ -345,13 +344,13 @@
for (unsigned i = 0, e = (*currentInstr_)->getNumOperands();
i != e; ++i) {
MachineOperand& op = (*currentInstr_)->getOperand(i);
- if (op.isVirtualRegister() && !op.opIsUse()) {
+ if (op.isVirtualRegister() && op.isDef()) {
unsigned virtReg = op.getAllocatedRegNum();
unsigned physReg = v2pMap_[virtReg];
if (!physReg) {
physReg = getFreeTempPhysReg(virtReg);
}
- if (op.opIsDefAndUse()) {
+ if (op.isUse()) { // def and use
loadVirt2PhysReg(virtReg, physReg);
}
else {
@@ -373,7 +372,7 @@
(*currentInstr_)->getOperand(1).getAllocatedRegNum()) {
assert((*currentInstr_)->getOperand(1).isRegister() &&
(*currentInstr_)->getOperand(1).getAllocatedRegNum() &&
- (*currentInstr_)->getOperand(1).opIsUse() &&
+ (*currentInstr_)->getOperand(1).isUse() &&
"Two address instruction invalid");
unsigned regA =
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.15 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.16
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.15 Tue Nov 11 16:41:32 2003
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Sun Dec 14 07:24:16 2003
@@ -118,8 +118,7 @@
MachineOperand &MO = (*I)->getOperand(i);
assert(!MO.isVirtualRegister() &&
"Register allocation must be performed!");
- if (MO.isPhysicalRegister() &&
- (MO.opIsDefOnly() || MO.opIsDefAndUse()))
+ if (MO.isPhysicalRegister() && MO.isDef())
ModifiedRegs[MO.getReg()] = true; // Register is modified
}
++I;
Index: llvm/lib/CodeGen/PHIElimination.cpp
diff -u llvm/lib/CodeGen/PHIElimination.cpp:1.13 llvm/lib/CodeGen/PHIElimination.cpp:1.14
--- llvm/lib/CodeGen/PHIElimination.cpp:1.13 Tue Nov 11 16:41:32 2003
+++ llvm/lib/CodeGen/PHIElimination.cpp Sun Dec 14 07:24:17 2003
@@ -175,7 +175,7 @@
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
MachineOperand &MO = PrevInst->getOperand(i);
if (MO.isVirtualRegister() && MO.getReg() == IncomingReg)
- if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
+ if (MO.isDef()) {
HaveNotEmitted = false;
break;
}
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.81 llvm/lib/CodeGen/MachineInstr.cpp:1.82
--- llvm/lib/CodeGen/MachineInstr.cpp:1.81 Tue Nov 11 16:41:32 2003
+++ llvm/lib/CodeGen/MachineInstr.cpp Sun Dec 14 07:24:17 2003
@@ -153,8 +153,8 @@
for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
if (*O == oldVal)
if (!defsOnly ||
- notDefsAndUses && O.isDefOnly() ||
- !notDefsAndUses && !O.isUseOnly())
+ notDefsAndUses && (O.isDef() && !O.isUse()) ||
+ !notDefsAndUses && O.isDef())
{
O.getMachineOperand().value = newVal;
++numSubst;
@@ -166,8 +166,8 @@
for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal)
if (!defsOnly ||
- notDefsAndUses && getImplicitOp(i).opIsDefOnly() ||
- !notDefsAndUses && !getImplicitOp(i).opIsUse())
+ notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) ||
+ !notDefsAndUses && getImplicitOp(i).isDef())
{
getImplicitOp(i).value = newVal;
++numSubst;
@@ -210,13 +210,13 @@
const TargetMachine &TM) {
const MRegisterInfo *MRI = TM.getRegisterInfo();
bool CloseParen = true;
- if (MO.opHiBits32())
+ if (MO.isHiBits32())
OS << "%lm(";
- else if (MO.opLoBits32())
+ else if (MO.isLoBits32())
OS << "%lo(";
- else if (MO.opHiBits64())
+ else if (MO.isHiBits64())
OS << "%hh(";
- else if (MO.opLoBits64())
+ else if (MO.isLoBits64())
OS << "%hm(";
else
CloseParen = false;
@@ -289,8 +289,7 @@
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
- if (getNumOperands() &&
- (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
+ if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
llvm::print(getOperand(0), OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
@@ -304,10 +303,11 @@
OS << " ";
llvm::print(mop, OS, TM);
- if (mop.opIsDefAndUse())
- OS << "<def&use>";
- else if (mop.opIsDefOnly())
- OS << "<def>";
+ if (mop.isDef())
+ if (mop.isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
// code for printing implicit references
@@ -316,10 +316,11 @@
for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
OS << "\t";
OutputValue(OS, getImplicitRef(i));
- if (getImplicitOp(i).opIsDefAndUse())
- OS << "<def&use>";
- else if (getImplicitOp(i).opIsDefOnly())
- OS << "<def>";
+ if (getImplicitOp(i).isDef())
+ if (getImplicitOp(i).isUse())
+ OS << "<def&use>";
+ else
+ OS << "<def>";
}
}
@@ -333,10 +334,11 @@
for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
- if (MI.getOperand(i).opIsDefOnly())
- os << "<d>";
- if (MI.getOperand(i).opIsDefAndUse())
- os << "<d&u>";
+ if (MI.getOperand(i).isDef())
+ if (MI.getOperand(i).isUse())
+ os << "<d&u>";
+ else
+ os << "<d>";
}
// code for printing implicit references
@@ -345,8 +347,11 @@
os << "\tImplicit: ";
for (unsigned z=0; z < NumOfImpRefs; z++) {
OutputValue(os, MI.getImplicitRef(z));
- if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
- if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
+ if (MI.getImplicitOp(z).isDef())
+ if (MI.getImplicitOp(z).isUse())
+ os << "<d&u>";
+ else
+ os << "<d>";
os << "\t";
}
}
@@ -356,13 +361,13 @@
std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO)
{
- if (MO.opHiBits32())
+ if (MO.isHiBits32())
OS << "%lm(";
- else if (MO.opLoBits32())
+ else if (MO.isLoBits32())
OS << "%lo(";
- else if (MO.opHiBits64())
+ else if (MO.isHiBits64())
OS << "%hh(";
- else if (MO.opLoBits64())
+ else if (MO.isLoBits64())
OS << "%hm(";
switch (MO.getType())
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.12 llvm/lib/CodeGen/LiveVariables.cpp:1.13
--- llvm/lib/CodeGen/LiveVariables.cpp:1.12 Fri Dec 12 19:20:58 2003
+++ llvm/lib/CodeGen/LiveVariables.cpp Sun Dec 14 07:24:17 2003
@@ -226,7 +226,7 @@
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.opIsUse() || MO.opIsDefAndUse()) {
+ if (MO.isUse()) {
if (MO.isVirtualRegister() && !MO.getVRegValueOrNull()) {
HandleVirtRegUse(getVarInfo(MO.getReg()), MBB, MI);
} else if (MO.isPhysicalRegister() &&
@@ -244,7 +244,7 @@
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
+ if (MO.isDef()) {
if (MO.isVirtualRegister()) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
Index: llvm/lib/CodeGen/LiveIntervals.cpp
diff -u llvm/lib/CodeGen/LiveIntervals.cpp:1.6 llvm/lib/CodeGen/LiveIntervals.cpp:1.7
--- llvm/lib/CodeGen/LiveIntervals.cpp:1.6 Sat Dec 13 05:11:01 2003
+++ llvm/lib/CodeGen/LiveIntervals.cpp Sun Dec 14 07:24:17 2003
@@ -293,7 +293,7 @@
if (!mop.isRegister())
continue;
- if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
+ if (mop.isDef()) {
unsigned reg = mop.getAllocatedRegNum();
if (reg < MRegisterInfo::FirstVirtualRegister)
handlePhysicalRegisterDef(mbb, mi, reg);
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