[llvm-commits] CVS: reopt/lib/BinInterface/LLVMTrace.cpp analyze.cpp construct.cpp emit.cpp select.cpp sparc9.cpp sparcbin.cpp sparcdis.cpp
Brian Gaeke
gaeke at cs.uiuc.edu
Wed Nov 19 16:52:01 PST 2003
Changes in directory reopt/lib/BinInterface:
LLVMTrace.cpp updated: 1.4 -> 1.5
analyze.cpp updated: 1.15 -> 1.16
construct.cpp updated: 1.10 -> 1.11
emit.cpp updated: 1.10 -> 1.11
select.cpp updated: 1.11 -> 1.12
sparc9.cpp updated: 1.8 -> 1.9
sparcbin.cpp updated: 1.14 -> 1.15
sparcdis.cpp updated: 1.17 -> 1.18
---
Log message:
Put reoptimizer code into 'llvm' namespace.
Other minor cleanups.
---
Diffs of the changes: (+37 -142)
Index: reopt/lib/BinInterface/LLVMTrace.cpp
diff -u reopt/lib/BinInterface/LLVMTrace.cpp:1.4 reopt/lib/BinInterface/LLVMTrace.cpp:1.5
--- reopt/lib/BinInterface/LLVMTrace.cpp:1.4 Fri Aug 22 12:43:37 2003
+++ reopt/lib/BinInterface/LLVMTrace.cpp Wed Nov 19 16:51:46 2003
@@ -18,13 +18,13 @@
using std::map;
using std::cerr;
using std::vector;
+using namespace llvm;
LLVMTrace::LLVMTrace(BinInterface *b,VirtualMem *v, TraceCache *t){
bb = b;
tr = t;
vm = v;
}
-
void LLVMTrace::addTrace(map<BasicBlock *, unsigned int> &bbToCid,
map<BasicBlock *, unsigned int> &bbToSec,
Index: reopt/lib/BinInterface/analyze.cpp
diff -u reopt/lib/BinInterface/analyze.cpp:1.15 reopt/lib/BinInterface/analyze.cpp:1.16
--- reopt/lib/BinInterface/analyze.cpp:1.15 Fri Oct 10 13:44:43 2003
+++ reopt/lib/BinInterface/analyze.cpp Wed Nov 19 16:51:46 2003
@@ -18,17 +18,7 @@
#include <cstdio>
#include <cassert>
-//*****************************************************************************
-// unsigned sparc_analyzebr(unsigned instr)
-//
-// Analyze instructions with OP field set to OP_BRANCH
-// (note not all of these instructions are branches!)
-//
-//
-// Returns a mask stating which parameters (RS1/RS2/etc) are present
-// and whether we write to CC, etc. See analyze.h
-//
-//*****************************************************************************
+using namespace llvm;
bool isFloatingPoint(unsigned instr){
if(RD_FLD(instr,INSTR_OP)==OP_2 && RD_FLD(instr, INSTR_OP3) == OP3_FPU){
@@ -83,6 +73,12 @@
return false;
}
+// unsigned sparc_analyzebr(unsigned instr)
+// Analyze instructions with OP field set to OP_BRANCH
+// (note not all of these instructions are branches!)
+// Returns a mask stating which parameters (RS1/RS2/etc) are present
+// and whether we write to CC, etc. See analyze.h
+//
unsigned sparc_analyzebr(unsigned instr)
{
if(RD_FLD(instr, INSTR_OP)==OP_CALL)
@@ -129,13 +125,9 @@
return 0;
}
-//*****************************************************************************
// unsigned sparc_analyze_c2(unsigned instr)
-//
// Analyze instructions with OP field set to OP_2
//
-//*****************************************************************************
-
unsigned sparc_analyze_c2(unsigned instr)
{
switch(RD_FLD(instr, INSTR_OP3))
@@ -191,8 +183,6 @@
else
return IF_RD| IF_RS1 | IF_RCC | IF_W_RD | IF_R_RS1;
-
-
case OP3_XNORcc:
case OP3_ANDNcc:
case OP3_ANDcc:
@@ -239,13 +229,9 @@
return 0;
}
-//*****************************************************************************
// unsigned sparc_analyze3(unsigned instr)
-//
// Analyze instructions with OP field set to OP_3
//
-//*****************************************************************************
-
unsigned sparc_analyze3(unsigned instr)
{
switch(RD_FLD(instr, INSTR_OP3))
@@ -303,13 +289,9 @@
return 0;
}
-//*****************************************************************************
// unsigned sparc_analyze_full(unsigned instr)
-//
// Analyze general instructions.
//
-//*****************************************************************************
-
unsigned sparc_analyze_full(unsigned instr)
{
if (RD_FLD(instr,INSTR_OP)==OP_2)
@@ -327,17 +309,13 @@
return 0;
}
-//*****************************************************************************
// unsigned sparc_analyze(unsigned instr)
-//
// Certain registers namely G0 (since writes don't take)
// must be ignored during dataflow analysis. Thus after
// running the full analysis pass we read all parameters
// that are marked as present - if the register is one of the
// banned ones we pretend that field isn't read.
//
-//*****************************************************************************
-
unsigned sparc_analyze(unsigned instr)
{
unsigned flags = sparc_analyze_full(instr);
@@ -359,15 +337,11 @@
return flags;
}
-//*****************************************************************************
// unsigned sparc_getwrites(unsigned mask, unsigned instr)
-//
// Mask is the result from sparc_analyze.
-//
// Returns a mask describing which registers were written to
// CC0 isn't in here.
//
-//*****************************************************************************
unsigned sparc_getwrites(unsigned mask, unsigned instr)
{
if (mask & IF_W_RD)
@@ -376,14 +350,10 @@
return 0;
}
-//*****************************************************************************
// unsigned sparc_getreads(unsigned mask, unsigned instr)
-//
// Mask is the result from sparc_analyze.
-//
// Returns a mask describing which registers were read from
//
-//*****************************************************************************
unsigned sparc_getreads (unsigned mask, unsigned instr)
{
unsigned m = 0;
@@ -400,26 +370,18 @@
return m;
}
-//*****************************************************************************
// unsigned sparc_getcc(unsigned mask, unsigned instr)
-//
// Mask is the result from sparc_analyze.
-//
// Returns the part of the mask strictly dealing with WCC or RCC
//
-//*****************************************************************************
-
-unsigned sparc_getcc (unsigned mask, unsigned instr)
+unsigned sparc_getcc (unsigned mask, unsigned instr)
{
return (mask & (IF_WCC | IF_RCC));
}
-//*****************************************************************************
// unsigned sparc_getbrdest(unsigned instr)
-//
// Returns the relative offset for the branch (in instruction words)
// eg 1 means 1 instruction forward.
-//
// Complete list of instructions that require relocation:
// BPr -> D16LO/D16HI field
// FBfcc -> DISP22 field (deprecated)
@@ -427,8 +389,7 @@
// Bicc -> DISP22 field (deprecated)
// BPcc -> DISP19 field
// CALL -> DISP30 field
-//*****************************************************************************
-
+//
signed sparc_getbrdest(unsigned instr)
{
if (RD_FLD(instr, INSTR_OP)==OP_CALL)
@@ -453,16 +414,11 @@
return 0;
}
-//*****************************************************************************
// unsigned sparc_setbrdest(unsigned instr, signed reladdr)
-//
// Modifies the relative destination of a given branch
//
-//*****************************************************************************
-
unsigned sparc_setbrdest(unsigned instr, signed reladdr)
{
-
if (RD_FLD(instr,INSTR_OP)==OP_CALL)
return MK_FLD(INSTR_OP, OP_CALL) |
MK_FLD(INSTR_DISP30, unsigned(reladdr) & 0x3FFFFFFF);
Index: reopt/lib/BinInterface/construct.cpp
diff -u reopt/lib/BinInterface/construct.cpp:1.10 reopt/lib/BinInterface/construct.cpp:1.11
--- reopt/lib/BinInterface/construct.cpp:1.10 Fri Oct 10 13:44:27 2003
+++ reopt/lib/BinInterface/construct.cpp Wed Nov 19 16:51:46 2003
@@ -18,6 +18,7 @@
using std::pair; // use STL pair class
using std::vector;
+using namespace llvm;
//for every liveout, create a livein node
//this makes sure a PHI node is created for every such node
Index: reopt/lib/BinInterface/emit.cpp
diff -u reopt/lib/BinInterface/emit.cpp:1.10 reopt/lib/BinInterface/emit.cpp:1.11
--- reopt/lib/BinInterface/emit.cpp:1.10 Fri Oct 10 13:44:27 2003
+++ reopt/lib/BinInterface/emit.cpp Wed Nov 19 16:51:46 2003
@@ -16,6 +16,7 @@
using std::pair;
using std::vector;
+using namespace llvm;
//*****************************************************************************
// prepare_exit(regalloc & regalloc,
Index: reopt/lib/BinInterface/select.cpp
diff -u reopt/lib/BinInterface/select.cpp:1.11 reopt/lib/BinInterface/select.cpp:1.12
--- reopt/lib/BinInterface/select.cpp:1.11 Fri Oct 10 13:44:55 2003
+++ reopt/lib/BinInterface/select.cpp Wed Nov 19 16:51:46 2003
@@ -16,6 +16,7 @@
#include <cassert>
using std::vector;
+using namespace llvm;
//*****************************************************************************
// select(regalloc & regs)
Index: reopt/lib/BinInterface/sparc9.cpp
diff -u reopt/lib/BinInterface/sparc9.cpp:1.8 reopt/lib/BinInterface/sparc9.cpp:1.9
--- reopt/lib/BinInterface/sparc9.cpp:1.8 Fri Aug 22 12:43:38 2003
+++ reopt/lib/BinInterface/sparc9.cpp Wed Nov 19 16:51:47 2003
@@ -6,6 +6,8 @@
#include "reopt/BinInterface/sparc9.h"
+namespace llvm {
+
const char * cc_names[] = { "fcc0", "fcc1", "fcc2", "fcc3",
"icc", "c101", "xcc", "c111"};
@@ -29,3 +31,4 @@
"O7", "L0", "L1", "L2", "L3", "L4", "L5", "L6",
"L7", "I0", "I1", "I2", "I3", "I4", "I5",
"I6(FP)", "I7"};
+} // end namespace llvm
Index: reopt/lib/BinInterface/sparcbin.cpp
diff -u reopt/lib/BinInterface/sparcbin.cpp:1.14 reopt/lib/BinInterface/sparcbin.cpp:1.15
--- reopt/lib/BinInterface/sparcbin.cpp:1.14 Fri Oct 10 13:44:55 2003
+++ reopt/lib/BinInterface/sparcbin.cpp Wed Nov 19 16:51:47 2003
@@ -20,35 +20,27 @@
#include <new>
using std::vector;
+using namespace llvm;
-//*****************************************************************************
// liveout(unsigned instr)
-//
// Marks an instruction liveout. Can only be called AFTER
// complete() and before reduce().
// Only values marked liveout will be in the original/correct
// register by end of epilog!
//
-//*****************************************************************************
void BinInterface::liveout(unsigned instr){
itable[instr]->flags |= IF_LIVEOUT;
}
-
-//*****************************************************************************
// emit(unsigned char * out)
-//
// Do register selection and emit the code
// The user supplies the buffer
// (user knows "max" size through a call to predict)
//
-//*****************************************************************************
-
unsigned BinInterface::emit(unsigned char * out){
// This structure receives the register allocation
// and spill register information to be passed
// on to the emitter.
- //
regalloc regs;
// Fill structure
@@ -58,26 +50,17 @@
return emit_gen(out, regs);
}
-//*****************************************************************************
// predict()
-//
// This function will correctly guess the largest size
// the buffer needs to be.
//
-//*****************************************************************************
-
unsigned BinInterface::predict(){
return (4 * itable.size() + 32*4) * sizeof(unsigned);
}
-
-//*****************************************************************************
// allocphi()
-//
// Allocate a PHI node from the user heap and link it in.
//
-//*****************************************************************************
-
instruction * BinInterface::allocphi(){
instruction * phi = new instruction();
phi->flags = IF_PHI;
@@ -88,21 +71,16 @@
return phi;
}
-//*****************************************************************************
// process_branch(
-//
// brdest[section] - the original address of the first instruction
// in that section
// scns - number of sections
// insertion i - the queued insertion command, contains the list
// of instructions
-//
// This function inserts the insertion into partial SSA instructions
// the only SSA fields that will be valid after this are the branch
// destinations
//
-//*****************************************************************************
-
void BinInterface::process_branch(const insertion & i,
unsigned ** brdest, int scns){
unsigned cid = i.idstart;
@@ -194,15 +172,11 @@
}
}
-//*****************************************************************************
// complete()
-//
// Since insertions into sections are queued (for branch resolution)
// this function is responsible for emptying the queues and inserting
// the instructions
//
-//*****************************************************************************
-
void BinInterface::complete(){
unsigned int p;
assert(sections.size() <= MAX_SECTIONS);
@@ -233,16 +207,11 @@
epToRetAddr.clear();
}
-//*****************************************************************************
// print(unsigned section)
-//
// For debug purposes only. Prints out a *SINGLE* section and its
// instructions in SSA form. Shows livein/liveout nodes as well
-//
// (must be called after reduce)
//
-//*****************************************************************************
-
void BinInterface::print(unsigned section){
unsigned u = begin(section);
@@ -295,13 +264,9 @@
}
}
-//*****************************************************************************
// print()
-//
// Prints all sections in SSA form
//
-//*****************************************************************************
-
void BinInterface::print(){
for (unsigned int p = 0; p< sections.size(); p++){
printf("Section %d\n",p);
@@ -309,30 +274,19 @@
}
}
-
-//*****************************************************************************
// newepilog()
-//
// Allocates a new epilog node and returns the instruction ID
//
-//*****************************************************************************
-
-
unsigned BinInterface::newepilog(){
unsigned v = sections.size();
push_section();
return v;
}
-
-//*****************************************************************************
// insert_instr(unsigned instr_id, instruction *instr)
-//
// Links instr into the linked list of instruction AFTER instr_id.
// instr->self must have been previously initialized
//
-//*****************************************************************************
-
void BinInterface::insert_instr(unsigned instr_id, instruction * instr){
unsigned a = instr_id;
unsigned c = itable[a]->next;
@@ -345,6 +299,7 @@
}
//remove an instruction cid
+//
void BinInterface::remove(unsigned cid){
instruction *instr = itable[cid];
@@ -362,6 +317,7 @@
}
//Move an instruction to after another instr
+//
void BinInterface::move_instr(unsigned instr_id, unsigned after_this){
instruction *instr = itable[instr_id];
//make sure it is not the ONLY instruction
@@ -380,6 +336,7 @@
}
//Move an instruction before another instr
+//
void BinInterface::move_instr_before(unsigned instr_id, unsigned before_this){
instruction *instr = itable[instr_id];
//make sure it is not the ONLY instruction
@@ -399,17 +356,15 @@
//Move an instruction to end the end of a section
+//
void BinInterface::moveToEnd(unsigned instr_id, unsigned section){
unsigned after_this = itable[end(section)]->prev;
move_instr(instr_id, after_this);
}
-//*****************************************************************************
// push_section()
-//
// Adds a new section. Initialized empty.
//
-//*****************************************************************************
void BinInterface::push_section(){
// create header node
instruction * instr = new instruction();
@@ -421,26 +376,20 @@
itable.push_back(instr);
}
-//*****************************************************************************
// BinInterface(unsigned heapsize)
// This constructor is used if code is to be read from, and is output into
// a buffer in the data region
//
-//*****************************************************************************
-
BinInterface::BinInterface(unsigned heapsize){
// create prolog and trace link nodes
push_section();
push_section();
}
-//*****************************************************************************
// BinInterface(unsigned heapsize)
// This constructor must be used if BinInterface
// must read and write into code region of executing program
//
-//*****************************************************************************
-
BinInterface::BinInterface(unsigned heapsize, VirtualMem *vmem,
TraceCache *trc){
// create prolog and trace link nodes
@@ -451,14 +400,10 @@
tr = trc;
}
-//*****************************************************************************
// allocnodelivein(int s, int reg)
-//
// Allocates a livein node and links it into the start of section 's'.
// the node is livein for given register. Instruction ID Is returned
//
-//*****************************************************************************
-
unsigned BinInterface::allocnodelivein(unsigned int s, unsigned int reg){
//check if livein doesn't already exist for this reg
for(vector<unsigned int>::iterator VI = livein.begin(), VE = livein.end();
@@ -477,16 +422,12 @@
return idx;
}
-//*****************************************************************************
// allocnodeshuffles(int s, fvector<shufflepair> * shuffles)
-//
// Allocates a shuffle node and links it into the start of section 's'.
// The shuffle node arranges for a set of SSA values to be in specific
// registers (used for liveout). Shuffles is a list of pairs of
// registers/instruction IDs.
//
-//*****************************************************************************
-
unsigned BinInterface::allocnodeshuffles(int s,
vector<shufflepair> * shuffles){
int idx = itable.size();
@@ -500,16 +441,11 @@
return idx;
}
-//*****************************************************************************
// insert(unsigned section, unsigned *ibegin, unsigned *iend)
-//
// Queues an contiguous series of instructions for insertion upon
// completion of the complete() function
-//
// NOTE: just like iterations iend is the first address NOT to insert.
//
-//*****************************************************************************
-
unsigned BinInterface::insert(unsigned section,
unsigned *ibegin, unsigned * iend){
// you're not allowed to have machine instructions
@@ -530,14 +466,10 @@
return i.idstart;
}
-//*****************************************************************************
// clear()
-//
// Reset the state of the binary interface so that we may compile a new
// trace (Very fast)
//
-//*****************************************************************************
-
void BinInterface::clear(){
itable.clear();
sections.clear();
@@ -549,20 +481,17 @@
push_section();
}
-//*****************************************************************************
// ~BinInterface()
-//
// The only memory that we don't manage in our allocator is the heap block
// itself. Thus the only object that needs destroyed
//
-//*****************************************************************************
-
BinInterface::~BinInterface()
{
//TODO
}
// Move instruction id to just after after_this
+//
void BinInterface::move(unsigned id, unsigned after_this){
instruction *instr = itable[id];
insert_instr(after_this, instr);
@@ -575,9 +504,10 @@
//INSTR_OP3 or INSTR_OP2: corresponding OPCODE
//INSTR_I = 0 (no immediate)
//Do not set rs1 or rs2, or the correspoding flags
-
+//
//We don't have to read RD_W because it'll get set automatically
//in select().
+//
unsigned BinInterface::newalu(unsigned op, unsigned rs1, unsigned rs2){
instruction *instr = new instruction();
//do not set the flags IF_R_RSx, and instead assign SSA values to
@@ -624,8 +554,8 @@
return cid;
}
-
//Create a NOP
+//
unsigned BinInterface::newnop(){
instruction *instr = new instruction();
instr->flags = (IF_ALUOP);
@@ -641,6 +571,7 @@
// New relative branch, destination is a section ID (returns
// branch instruction ID)
//rs1 is SSAid of register value on which branch condition is determined
+//
unsigned BinInterface::newbranch(unsigned op, unsigned rs1, unsigned dest){
instruction *instr = new instruction();
@@ -660,6 +591,7 @@
// New relative branch, destination is a section ID (returns
// branch instruction ID)
// NO rs1
+//
unsigned BinInterface::newbranch(unsigned op, unsigned dest){
instruction *instr = new instruction();
@@ -677,6 +609,7 @@
// New relative branch, destination is a absolute address (returns
// branch instruction ID)
// rs1 is SSAid of register value on which branch condition is determined
+//
unsigned BinInterface::newabsbranch(unsigned op, unsigned rs1, unsigned *dest){
instruction *instr = new instruction();
@@ -695,6 +628,7 @@
// New relative branch, destination is a section ID (returns
// branch instruction ID)
// NO rs1
+//
unsigned BinInterface::newabsbranch(unsigned op, unsigned *dest){
instruction *instr = new instruction();
@@ -709,10 +643,9 @@
return cid;
}
-
-
//set the branch as internal
//dest is the desctination section
+//
void BinInterface::setBranchAsInternal(unsigned cid, unsigned dest){
instruction *instr = itable[cid];
assert(instr->flags & IF_BR && "Not a branch\n");
@@ -720,8 +653,8 @@
instr->ibranch.dest = dest;
}
-
//reverse the branch condition
+//
void BinInterface::reverseBranch(unsigned cid){
instruction *instr = itable[cid];
assert(instr->flags & IF_BR && "Not a branch\n");
@@ -730,6 +663,7 @@
//change the branch destination
//should be called ONLY AFTER complete()
+//
void BinInterface::setBranchDest(unsigned cid, unsigned int *dest){
instruction *instr = itable[cid];
assert(instr->flags & IF_BR && "Not a branch\n");
@@ -738,6 +672,7 @@
}
//assign return addr to epilog
+//
void BinInterface::assignRetAdress(unsigned int sec, unsigned int *addr){
assert(sec > 1 && "Not a trace section or a prolog");
epToRetAddr[sec] = addr;
@@ -748,6 +683,7 @@
//for a given instruction is preserved: the instruction
//pinned down writes into the same register it originally wrote into
//however, the incoming registers might still be changed
+//
void BinInterface::pinDown(unsigned int pin){
if(itable[pin]->flags & IF_W_RD)
pinned.push_back(pin);
Index: reopt/lib/BinInterface/sparcdis.cpp
diff -u reopt/lib/BinInterface/sparcdis.cpp:1.17 reopt/lib/BinInterface/sparcdis.cpp:1.18
--- reopt/lib/BinInterface/sparcdis.cpp:1.17 Fri Oct 10 13:44:43 2003
+++ reopt/lib/BinInterface/sparcdis.cpp Wed Nov 19 16:51:47 2003
@@ -24,6 +24,8 @@
#include <cstdio>
#include <cassert>
+using namespace llvm;
+
void sparc_printop_rs1(unsigned instr, int labelrs1)
{
if (labelrs1)
@@ -270,7 +272,6 @@
return;
}
-
case OP3_ADD:
sparc_printalu("ADD", instr, labels,
labelrs1, labelrs2, labelrd, labelccf);
@@ -563,6 +564,7 @@
printf("+%d", SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
}
}
+
void sparc_print3(unsigned instr, bool labels, int labelrs1, int labelrs2,
int labelrd, int labelccf)
{
@@ -699,8 +701,6 @@
assert(0);
}
-
-
void sparc_print_pseudo(unsigned instr, int labelrs1, int labelrs2, int labelrd, int labelccf)
{
if (RD_FLD(instr,INSTR_OP)==OP_CALL)
@@ -724,6 +724,3 @@
else if (RD_FLD(instr,INSTR_OP)==OP_3)
sparc_print3(instr,false,0, 0, 0, 0 );
}
-
-
-
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