[llvm-commits] CVS: reopt/lib/Inst/lib/ElfReader.cpp InstManip.cpp InstManip.h PhaseInfo.h Phases.cpp SparcInstManip.cpp SparcInstManip.h
Brian Gaeke
gaeke at cs.uiuc.edu
Wed Nov 19 14:51:03 PST 2003
Changes in directory reopt/lib/Inst/lib:
ElfReader.cpp updated: 1.14 -> 1.15
InstManip.cpp updated: 1.15 -> 1.16
InstManip.h updated: 1.18 -> 1.19
PhaseInfo.h updated: 1.10 -> 1.11
Phases.cpp updated: 1.38 -> 1.39
SparcInstManip.cpp updated: 1.21 -> 1.22
SparcInstManip.h updated: 1.16 -> 1.17
---
Log message:
Cleanups: file headers, using declarations, namespacification, removing
#if 0'd-out code, wrapping at 80 columns, sorting headers, not using endl,
doxygenifying comments, renaming header guard macros, etc. (There is still
more to do, but at least it compiles again now...)
---
Diffs of the changes: (+488 -388)
Index: reopt/lib/Inst/lib/ElfReader.cpp
diff -u reopt/lib/Inst/lib/ElfReader.cpp:1.14 reopt/lib/Inst/lib/ElfReader.cpp:1.15
--- reopt/lib/Inst/lib/ElfReader.cpp:1.14 Fri Oct 10 13:45:21 2003
+++ reopt/lib/Inst/lib/ElfReader.cpp Wed Nov 19 14:49:52 2003
@@ -1,13 +1,20 @@
-////////////////
-// programmer: Joel Stanley
-// date: Fri Mar 21 16:11:07 CST 2003
-// fileid: ElfReader.cpp
-// purpose: Implementation of ELF reader interface as described in ElfReader.h. Note
-// that special care is taken to ensure that archive files are treated the same as
-// single object files.
+//===- ElfReader.cpp - ELF object file reader implementation --------------===//
+//
+// The LLVM Compiler Infrastructure
//
-// []
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Originally written by Joel Stanley on 21-Mar-2003. Implementation
+// of ELF reader interface as described in ElfReader.h. Note that
+// special care is taken to ensure that archive files are treated the
+// same as single object files.
+//
+//===----------------------------------------------------------------------===//
+#include "reopt/Inst/ElfReader.h"
#include <ar.h>
#include <fcntl.h>
#include <cstdio>
@@ -19,14 +26,12 @@
#include <iostream>
#include <iomanip>
-#include "reopt/Inst/ElfReader.h"
-
-using std::cerr;
-using std::endl;
-
-// Symbol binding values that don't occur in the ELF spec, but that are recognized as WEAK
-// and GLOB by the elfdump command-line utility. For matching output.
+using namespace llvm;
+/// Symbol binding values that don't occur in the ELF spec, but that
+/// are recognized as WEAK and GLOB by the elfdump command-line
+/// utility. For matching output.
+///
#define ELFDUMP_GLOB 0x10
#define ELFDUMP_WEAK 0x20
@@ -49,7 +54,7 @@
assert(m_fd != -1 && "Failed to open executable image");
if(elf_version(EV_CURRENT) == EV_NONE) {
- cerr << "ELF library version mismatch" << endl;
+ std::cerr << "ELF library version mismatch\n";
exit(1);
}
@@ -57,13 +62,9 @@
m_pPrimaryElf = elf_begin(m_fd, m_currCmd, 0);
assert(m_pPrimaryElf && "Failed to obtain primary ELF descriptor");
- // Advance to the first file in the archive (essentially a no-op if only one file)
+ // Advance to the first file in the archive (essentially a no-op
+ // if only one file)
m_pCurrElf = elf_begin(m_fd, m_currCmd, m_pPrimaryElf);
-
-#if 0
- if(Elf_Arhdr* arhdr = elf_getarhdr(m_pCurrElf))
- cerr << "AR member name: " << arhdr->ar_name << endl;
-#endif
}
ElfReader::~ElfReader()
@@ -72,12 +73,13 @@
close(m_fd);
}
+/// Print the given symbol table entry. Output format is similar to
+/// that of the elfdump command line utility.
+///
void ElfReader::printSymTableEntry(Elf64_Sym* sym, std::ostream& ostr)
{
- // Print this symbol table entry. Output format is similar to that of the elfdump
- // command line utility.
-
- ostr << std::setw(16) << std::hex << std::setfill('0') << sym->st_value << " "
+ ostr << std::setw(16) << std::hex << std::setfill('0') << sym->st_value
+ << " "
<< std::setw(16) << std::hex << std::setfill('0') << sym->st_size;
int type = sym->st_info & 0xf;
@@ -98,7 +100,7 @@
ostr << "OTHR"; break;
default:
- //ostr << "(" << type << ")" << endl;
+ ostr << "Offending type: (" << type << ")\n";
assert(0 && "Symbol table entry has unknown type");
break;
}
@@ -122,7 +124,7 @@
ostr << "OTHR"; break;
default:
- //ostr << "(" << binding << ")" << endl;
+ ostr << "Offending type: (" << binding << ")\n";
assert(0 && "Unknown binding type");
break;
}
@@ -151,7 +153,7 @@
}
// Output symbol name
- ostr << " " << (m_pStrTab + sym->st_name) << endl;
+ ostr << " " << (m_pStrTab + sym->st_name) << "\n";
}
void ElfReader::nextFile()
@@ -159,17 +161,10 @@
// Advance to the next file in the archive.
m_currCmd = elf_next(m_pCurrElf);
- // Dispose of the old ELF descriptor and get a new one that corresponds to the new
- // file in the archive.
-
+ // Dispose of the old ELF descriptor and get a new one that
+ // corresponds to the new file in the archive.
elf_end(m_pCurrElf);
m_pCurrElf = elf_begin(m_fd, m_currCmd, m_pPrimaryElf);
-
-#if 0
- if(Elf_Arhdr* arhdr = elf_getarhdr(m_pCurrElf))
- cerr << "AR member name: " << arhdr->ar_name << endl;
-#endif
-
m_pElfHdr = 0;
m_pSymHdr = 0;
m_pSymSec = 0;
@@ -189,8 +184,10 @@
return false;
// Obtain pointer to the string table of section names
- Elf_Data* strTabHand = elf_getdata(elf_getscn(m_pCurrElf, m_pElfHdr->e_shstrndx), 0);
- assert(strTabHand && "Couldn't obtain ELF data handle to section-name string table");
+ Elf_Data* strTabHand =
+ elf_getdata(elf_getscn(m_pCurrElf, m_pElfHdr->e_shstrndx), 0);
+ assert(strTabHand
+ && "Couldn't obtain ELF data handle to section-name string table");
m_pSecNameTab = (char*) strTabHand->d_buf;
// Find symbol table(s), etc.
@@ -198,7 +195,8 @@
// Obtain pointer to string table associated with the symbol table
strTabHand = elf_getdata(elf_getscn(m_pCurrElf, m_pSymHdr->sh_link), 0);
- assert(strTabHand && "Couldn't obtain ELF data handle to symbol-name string table");
+ assert(strTabHand
+ && "Couldn't obtain ELF data handle to symbol-name string table");
m_pStrTab = (char*) strTabHand->d_buf;
assert(m_pSymHdr->sh_entsize == sizeof(Elf64_Sym) &&
@@ -206,14 +204,17 @@
// Determine the number of entries in the table
Elf64_Xword numEntries = m_pSymHdr->sh_size / sizeof(Elf64_Sym);
- assert(m_pSymHdr->sh_size % sizeof(Elf64_Sym) == 0 && "Symtable size must be multiple of entry size");
+ assert(m_pSymHdr->sh_size % sizeof(Elf64_Sym) == 0
+ && "Symtable size must be multiple of entry size");
assert(m_pSymHdr->sh_size > 0 && "Empty symbol table encountered");
// Obtain the symbol table data
Elf_Data* data = elf_getdata(m_pSymSec, 0);
assert(data && "Could not obtain symtable data");
- assert(data->d_size == m_pSymHdr->sh_size && "Size in data and size in header do not correspond");
- assert(data->d_type == ELF_T_SYM && "Unexpected data type found in symtable");
+ assert(data->d_size == m_pSymHdr->sh_size
+ && "Size in data and size in header do not correspond");
+ assert(data->d_type == ELF_T_SYM
+ && "Unexpected data type found in symtable");
assert(!elf_getdata(m_pSymSec, data) && "No more data expected in section");
// Set current entry pointer and pointer to end of table
@@ -233,10 +234,10 @@
}
if(!m_pElfHdr) {
- // No ELF header? Must be about to process a new file in the archive. Perform the
- // necessary setup that must occur before processing. If handling the current
- // new file fails, try the next one.
-
+ // No ELF header? Must be about to process a new file in the
+ // archive. Perform the necessary setup that must occur before
+ // processing. If handling the current new file fails, try the
+ // next one.
if(!handleNewFile()) {
nextFile();
return findNextSymbol(fname, range, instWidth);
@@ -245,25 +246,23 @@
assert(m_pCurrSym && m_pSymEnd && "Invalid symtable pointers");
- // Locate next function (skipping non-function entries) in the symbol table that is
- // marked as being in the code segment. If found, return true, yielding name & extents
- // by reference. If we are done scanning the symbol table, advance to the next file in
+ // Locate next function (skipping non-function entries) in the
+ // symbol table that is marked as being in the code segment. If
+ // found, return true, yielding name & extents by reference. If we
+ // are done scanning the symbol table, advance to the next file in
// the archive and continue searching recursively.
-
bool foundSym = false;
for( ; !foundSym && m_pCurrSym != m_pSymEnd; ++m_pCurrSym) {
- unsigned info = m_pCurrSym->st_info & 0xf; // Symbol type is lower 4 bits
-
+ unsigned info = m_pCurrSym->st_info & 0xf; // Sym. type is lower 4 bits
if(STT_FUNC == info && m_pCurrSym->st_shndx == m_codeSecIdx) {
- //printSymTableEntry(m_pCurrSym);
-
fname = m_pStrTab + m_pCurrSym->st_name;
- // NB: Address range contains the (closed) memory interval [start,end] of
- // the memory addresses of function with symbol fname.
-
+ // NB: Address range contains the (closed) memory interval
+ // [start,end] of the memory addresses of function with
+ // symbol fname.
range.first = m_pCurrSym->st_value;
- range.second = m_pCurrSym->st_value + m_pCurrSym->st_size - instWidth;
+ range.second = m_pCurrSym->st_value + m_pCurrSym->st_size
+ - instWidth;
foundSym = true;
}
}
@@ -276,12 +275,13 @@
return findNextSymbol(fname, range, instWidth);
}
+/// Examine the section header of each section, looking for the symbol
+/// table (which must be unique, otherwise a runtime error occurs) and
+/// the code segment, i.e., the segment which has the spec-defined
+/// name ".text".
+///
void ElfReader::locateSections()
{
- // Examine the section header of each section, looking for:
- // a) The symbol table. When found ensure that it is unique, otherwise, assert out.
- // b) The code segment (i.e. the segment which has the spec-defined name ".text"
-
bool codeSegmentFound = false;
Elf64_Shdr* secHdr;
for(Elf_Scn* currScn = 0; (currScn = elf_nextscn(m_pCurrElf, currScn)); ) {
@@ -290,13 +290,15 @@
if(SHT_SYMTAB == secHdr->sh_type) {
// Found section marked as a symbol table
- assert(!m_pSymHdr && !m_pSymSec && "Should only be one symbol table in the image");
+ assert(!m_pSymHdr && !m_pSymSec
+ && "Should only be one symbol table in the image");
m_pSymHdr = secHdr;
m_pSymSec = currScn;
}
else if(SHT_PROGBITS == secHdr->sh_type && !codeSegmentFound) {
- // Found section marked as "program-defined". Obtain section name and see
- // if it matches the name of the code segment.
+ // Found section marked as "program-defined". Obtain
+ // section name and see if it matches the name of the code
+ // segment.
char* sectionName = m_pSecNameTab + secHdr->sh_name;
if(sm_codeSegmentName == sectionName) {
m_codeSecIdx = elf_ndxscn(currScn);
@@ -308,6 +310,5 @@
assert(m_pSymHdr && m_pSymSec &&
"Couldn't locate symbol table (stripped executable?)");
-
assert(codeSegmentFound && "Couldn't locate code segment");
}
Index: reopt/lib/Inst/lib/InstManip.cpp
diff -u reopt/lib/Inst/lib/InstManip.cpp:1.15 reopt/lib/Inst/lib/InstManip.cpp:1.16
--- reopt/lib/Inst/lib/InstManip.cpp:1.15 Sat Sep 13 16:12:07 2003
+++ reopt/lib/Inst/lib/InstManip.cpp Wed Nov 19 14:49:52 2003
@@ -1,20 +1,25 @@
-////////////////
-// programmer: Joel Stanley
-// date: Tue Apr 8 22:45:53 CDT 2003
-// fileid: InstManip.cpp
-// purpose: Implements the InstManip class as described in InstManip.h.
-
-#include <iostream>
-#include <iomanip>
-#include <cassert>
+//===- InstManip.cpp - InstManip class implementation ---------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Originally written by Joel Stanley on 8-Apr-2003. Implements the
+// InstManip class as described in InstManip.h.
+//
+//===----------------------------------------------------------------------===//
#include "reopt/TraceCache.h"
#include "reopt/VirtualMem.h"
#include "InstManip.h"
+#include <iostream>
+#include <iomanip>
+#include <cassert>
-using std::cout;
-using std::cerr;
-using std::endl;
+namespace llvm {
std::ostream& operator<<(std::ostream& ostr,
const InstCandidate& cand)
@@ -25,17 +30,17 @@
void InstCandidate::print(std::ostream& ostr) const
{
- ostr << "InstCandidate {" << endl;
- ostr << " type = "
- << (m_type == DIRECT ? "DIRECT" : "STACK XFER")
- << endl;
- ostr << " Instruction dump (address, inst):" << endl;
+ ostr << "InstCandidate {\n"
+ << " type = "
+ << (m_type == DIRECT ? "DIRECT" : "STACK XFER")
+ << "\n"
+ << " Instruction dump (address, inst):\n";
for(std::vector<std::pair<uint64_t, unsigned> >::const_iterator i =
m_insts.begin(), e = m_insts.end(); i != e; ++i) {
ostr << std::hex << " (" << i->first << ", " << std::flush;
m_pIM->printInst(i->second);
- ostr << ")" << endl;
+ ostr << ")\n";
}
ostr << "}";
}
@@ -60,17 +65,19 @@
delete [] m_pPhase3SpillRegion;
}
+/// Heap-allocate a region of memory in which to spill shared
+/// registers before phase3 invocations. We allocate one unit of
+/// space (given by getSharedSize()) for each function that must be
+/// transformed.
+///
void InstManip::makePhase3SpillRegion(unsigned numFuncs)
{
- // Heap-allocate a region of memory in which to spill shared registers before phase3
- // invocations. We allocate one unit of space (given by getSharedSize()) for each
- // function that must be transformed.
-
m_pPhase3SpillRegion = new uint64_t[getSharedSize() * numFuncs];
m_pCurrSpill = m_pPhase3SpillRegion;
}
-void InstManip::copySnippetToSlot(std::vector<unsigned>& snippet, uint64_t slotBase)
+void InstManip::copySnippetToSlot(std::vector<unsigned>& snippet,
+ uint64_t slotBase)
{
uint64_t currAddr = slotBase;
for(std::vector<unsigned>::iterator i = snippet.begin(),
@@ -79,3 +86,5 @@
currAddr += getInstWidth();
}
}
+
+} // end namespace llvm
Index: reopt/lib/Inst/lib/InstManip.h
diff -u reopt/lib/Inst/lib/InstManip.h:1.18 reopt/lib/Inst/lib/InstManip.h:1.19
--- reopt/lib/Inst/lib/InstManip.h:1.18 Sun May 18 12:45:25 2003
+++ reopt/lib/Inst/lib/InstManip.h Wed Nov 19 14:49:53 2003
@@ -1,32 +1,43 @@
-////////////////
-// programmer: Joel Stanley
-// date: Tue Apr 8 22:42:14 CDT 2003
-// fileid: InstManip.h
-// purpose: InstManip is a (pure virtual) class that hdies platform-specific
-// instruction manipulation behind a common interface, and provides clients with
-// various instruction manipulation utilities. Since the structure of the TraceCache
-// "slots" for the various phases of the binary editing for performance
-// instrumentation have structure and content that is platform-dependent, this class
-// also hides the platform-specific details of the slot construction as well. Only
-// two relevant assumptions are made:
+//===- InstManip.cpp - InstManip class interface --------------------------===//
+//
+// The LLVM Compiler Infrastructure
//
-// * The TraceCache objects (TraceCache, MemoryManager, VirtualMem, etc) from the
-// Reoptimizer library work in an appropriate manner on the given platform.
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
//
-// * uint64_t is used for addresses, and unsigned is used for instruction words.
+// Originally written by Joel Stanley on 8-Apr-2003. InstManip is a (pure
+// virtual) class that hides platform-specific instruction manipulation behind a
+// common interface, and provides clients with various instruction manipulation
+// utilities. Since the structure of the TraceCache "slots" for the various
+// phases of the binary editing for performance instrumentation have structure
+// and content that is platform-dependent, this class also hides the
+// platform-specific details of the slot construction as well. Only two
+// relevant assumptions are made:
//
-// Better parameterization of type attributes (perhaps by making it a template class?)
-// is on the TODO list. This is currently difficult because the aforementioned
-// Reoptimizer classes are not parameterized.
+// * The TraceCache objects (TraceCache, MemoryManager, VirtualMem, etc) from
+// the Reoptimizer library work in an appropriate manner on the given
+// platform.
+//
+// * uint64_t is used for addresses, and unsigned is used for instruction
+// words.
+//
+// Better parameterization of type attributes (perhaps by making it a template
+// class?) is on the TODO list. This is currently difficult because the
+// aforementioned Reoptimizer classes are not parameterized.
+//
+//===----------------------------------------------------------------------===//
-#ifndef _INCLUDED_INSTMANIP_H
-#define _INCLUDED_INSTMANIP_H
+#ifndef INSTMANIP_H
+#define INSTMANIP_H
+#include "Phase1/Intraphase.h"
#include <algorithm>
#include <map>
#include <vector>
-#include "Phase1/Intraphase.h"
+namespace llvm {
class TraceCache;
class Phase2;
@@ -49,8 +60,9 @@
typedef std::pair<uint64_t, uint64_t> AddressRange;
- // Logical registers used by clients of this class, mapped to machine-specific IDs
- // by the logical -> actual register map.
+ /// Logical registers used by clients of this class, mapped to
+ /// machine-specific IDs by the logical -> actual register map.
+ ///
enum LogicalRegister {
REG_0,
REG_1,
@@ -58,10 +70,12 @@
REG_7
};
- // buildSlot - Fill the provided vector with the instructions that go into the slot
- // given by the Phase{3,4}Info instance. The proper function is distinguished by type
- // in this manner because there are not really enough phases to warrant building the
- // slot-building behavior into the Phase{3,4}Info classes themselves.
+ /// buildSlot - Fill the provided vector with the instructions that go into
+ /// the slot given by the Phase{3,4}Info instance. The proper function is
+ /// distinguished by type in this manner because there are not really enough
+ /// phases to warrant building the slot-building behavior into the
+ /// Phase{3,4}Info classes themselves.
+ ///
// For the phase 3 slot
virtual void buildSlot(Phase3Info* p3info,
@@ -82,30 +96,30 @@
virtual unsigned getSlotSize(Phase3* p3, InstCandidate& cand) const = 0;
virtual unsigned getSlotSize(Phase4* p4) const = 0;
- // findCandidates - Build the vector of instruction candidates that occur in the
- // region defined by the given addresses. This is necessarily a platform-dependent
- // action.
-
+ /// findCandidates - Build the vector of instruction candidates that occur
+ /// in the region defined by the given addresses. This is necessarily a
+ /// platform-dependent action.
+ ///
virtual void findCandidates(const std::pair<uint64_t, uint64_t>& range,
std::vector<InstCandidate>& candidates) = 0;
- // getStartAddr - return the desired starting position in the function body. This is
- // useful for skipping standard prologue code that occurs at the start of the function
- // body.
-
+ /// getStartAddr - return the desired starting position in the function
+ /// body. This is useful for skipping standard prologue code that occurs at
+ /// the start of the function body.
+ ///
virtual uint64_t getStartAddr(uint64_t funcStartAddr) const = 0;
- virtual unsigned getBranchAlways(uint64_t dest, uint64_t pc, bool annulHigh = true) const = 0;
+ virtual unsigned getBranchAlways(uint64_t dest, uint64_t pc,
+ bool annulHigh = true) const = 0;
virtual bool isBranch(unsigned inst) const = 0;
virtual void printRange(unsigned* start, unsigned* end) const = 0;
virtual void printInst(unsigned inst) const = 0;
- ////
-
void makePhase3SpillRegion(unsigned numFuncs);
uint64_t* getCurrentSpill() { return m_pCurrSpill; }
void advanceSpill() { m_pCurrSpill += getSharedSize(); }
- void copySnippetToSlot(std::vector<unsigned>& snippet, uint64_t slotBase);
+ void copySnippetToSlot(std::vector<unsigned>& snippet,
+ uint64_t slotBase);
inline void printRange(uint64_t start, uint64_t end) const;
@@ -118,15 +132,19 @@
typedef std::map<LogicalRegister, unsigned> LogicalToActualRegMap;
- LogicalToActualRegMap m_logicalToActualReg; // Maps logical -> actual register
+ // Maps logical -> actual register
+ LogicalToActualRegMap m_logicalToActualReg;
TraceCache* m_pTC;
-
- uint64_t* m_pPhase3SpillRegion; // Base pointer to spill region for phase 3 invocations
- uint64_t* m_pCurrSpill; // Current location in the phase 3 spill region
-
- unsigned m_sharedSize; // # of shared registers that must be spilled
- unsigned m_instWidth; // instruction width, in bytes
- unsigned m_nopInst; // NOP instruction word
+ // Base pointer to spill region for phase 3 invocations
+ uint64_t* m_pPhase3SpillRegion;
+ // Current location in the phase 3 spill region
+ uint64_t* m_pCurrSpill;
+ // # of shared registers that must be spilled
+ unsigned m_sharedSize;
+ // instruction width, in bytes
+ unsigned m_instWidth;
+ // NOP instruction word
+ unsigned m_nopInst;
};
void InstManip::printRange(uint64_t start, uint64_t end) const
@@ -134,14 +152,13 @@
printRange((unsigned*) start, (unsigned*) end);
}
-////////////////
-
-// InstCandidate is a class that represents a location in the code that is determined to
-// be a candidate for instrumentation. Because the transformation action required for a
-// particular candidate requires auxiliary information (such as other instructions found
-// within the region of the primary candidate instruction), these are encapsulated in the
-// InstCandidate as well.
-
+/// InstCandidate is a class that represents a location in the code that is
+/// determined to be a candidate for instrumentation. Because the
+/// transformation action required for a particular candidate requires auxiliary
+/// information (such as other instructions found within the region of the
+/// primary candidate instruction), these are encapsulated in the InstCandidate
+/// as well.
+///
class InstCandidate
{
public:
@@ -186,12 +203,14 @@
InstManip* m_pIM;
CandType m_type;
- // Each element of this vector holds a (address, inst) pair.
+ /// Each element of this vector holds a (address, inst) pair.
+ ///
std::vector<std::pair<uint64_t, unsigned> > m_insts;
-
};
std::ostream& operator<<(std::ostream& ostr, const InstCandidate& cand);
-#endif // _INCLUDED_INSTMANIP_H
+}; // end namespace llvm
+
+#endif // INSTMANIP_H
Index: reopt/lib/Inst/lib/PhaseInfo.h
diff -u reopt/lib/Inst/lib/PhaseInfo.h:1.10 reopt/lib/Inst/lib/PhaseInfo.h:1.11
--- reopt/lib/Inst/lib/PhaseInfo.h:1.10 Tue Jun 24 10:39:52 2003
+++ reopt/lib/Inst/lib/PhaseInfo.h Wed Nov 19 14:49:53 2003
@@ -1,14 +1,24 @@
-////////////////
-// programmer: Joel Stanley
-// date: Tue Apr 29 23:02:12 CDT 2003
-// fileid: PhaseInfo.h
-// purpose: Describes the classes that are used to carry information between
-// phases.
+//===- PhaseInfo.h - Classes carrying info between phases -----------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Originally written by Joel Stanley on 29-Apr-2003. Describes the
+// classes that are used to carry information between phases.
+//
+//===----------------------------------------------------------------------===//
-#ifndef _INCLUDED_PHASEINFO_H
-#define _INCLUDED_PHASEINFO_H
+#ifndef PHASEINFO_H
+#define PHASEINFO_H
#include "InstManip.h"
+#include <iostream>
+
+namespace llvm {
class TraceCache;
class InstManip;
@@ -54,12 +64,12 @@
void print(std::ostream& ostr)
{
- ostr << std::hex << "Phase3Info instance: {" << std::endl
+ ostr << std::hex << "Phase3Info instance: {\n"
<< " Function address range: [" << m_range.first << ", "
- << m_range.second << "]" << std::endl
+ << m_range.second << "]\n"
<< " To replace: [" << m_origInst << " @ "
- << m_replaceAddr << "]" << std::endl
- << "}" << std::endl;
+ << m_replaceAddr << "]\n"
+ << "}\n";
}
const AddressRange& getRange() const { return m_range; }
@@ -79,7 +89,7 @@
uint64_t m_slotDescriptor; // Slot created by phase 2
unsigned m_slotSize; // Size of slot created by phase 2
TraceCache* m_pTC; // TraceCache instance used by phase 2
- InstManip* m_pIM; // The InstManip instance to pass to the next phase
+ InstManip* m_pIM; // InstManip instance passed to next phase
};
class Phase4Info
@@ -101,7 +111,7 @@
}
const InstCandidate& getCandidate() const { return m_candidate; }
- const AddressRange& getRange() const { return m_range; }
+ const AddressRange& getRange() const { return m_range; }
uint64_t getSlot() const { return m_slotDescriptor; }
uint64_t getSlotSize() const { return m_slotSize; }
TraceCache* getTraceCache() { return m_pTC; }
@@ -110,12 +120,25 @@
private:
Phase4Info() {}
- InstCandidate m_candidate; // Candidate responsible for this instance's creation
- AddressRange m_range; // Start address of enclosing function
- uint64_t m_slotDescriptor; // Slot created by phase 3
- unsigned m_slotSize; // Size of slot created by phase 3
- TraceCache* m_pTC; // TraceCache instance used by phases 2 and 3
- InstManip* m_pIM; // The InstManip instance to pass to the next phase
+ // Candidate responsible for this instance's creation
+ InstCandidate m_candidate;
+
+ // Start address of enclosing function
+ AddressRange m_range;
+
+ // Slot created by phase 3
+ uint64_t m_slotDescriptor;
+
+ // Size of slot created by phase 3
+ unsigned m_slotSize;
+
+ // TraceCache instance used by phases 2 and 3
+ TraceCache* m_pTC;
+
+ // The InstManip instance to pass to the next phase
+ InstManip* m_pIM;
};
-#endif // _INCLUDED_PHASEINFO_H
+} // end namespace llvm
+
+#endif // PHASEINFO_H
Index: reopt/lib/Inst/lib/Phases.cpp
diff -u reopt/lib/Inst/lib/Phases.cpp:1.38 reopt/lib/Inst/lib/Phases.cpp:1.39
--- reopt/lib/Inst/lib/Phases.cpp:1.38 Sat Sep 13 16:12:07 2003
+++ reopt/lib/Inst/lib/Phases.cpp Wed Nov 19 14:49:53 2003
@@ -1,58 +1,64 @@
-////////////////
-// programmer: Joel Stanley
-// date: Fri Apr 4 16:59:48 CST 2003
-// fileid: Phases.cpp
-// purpose: Implements runtime phases 2-5 of the peformance-oriented language
-// extensions.
-//
-// PHASE 2:
-// On program startup ("phase 2" function called from main()):
-//
-// 1. Read the neccessary ELF data associated with the executable image.
-//
-// 2. For each function F (in section labelled ".text"), write code to call phase 3.
-//
-// 2a. Replace the first (replacable) instruction in F with a branch to a new
-// slot (annulling bit should specify *not* to execute the branch delay slot) in
-// the dummy function.
-//
-// 2b. In the new slot, write the contents of the phase 3 slot (see appropriate
-// InstManip instance for detailed information about slot contents).
-//
-// PHASE 3:
-//
-// - Deallocate the parameter structure whenever it is convenient to do so.
-//
-// 1. Replace the original (replaced) instruction at the proper location in the
-// original code.
-//
-// 2. Analyze the function and determine the load-volatile candidates.
-//
-// 3. For each load-volatile candidate,
-// 3a. Obtain a new slot in the dummy function.
-// 3b. Replace the load candidate with branch to slot.
-// 3c. In the new slot, write the contents of the phase 4 slot (see appropriate
-// InstManip instance for detailed information about slot contents).
-//
-// 4. Deallocate the slot that originated this invocation of phase3().
+//===- Phases.cpp - Implements phases 2-5 of performance-oriented extensions =//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Originally written by Joel Stanley on 4-Apr-2003. Implements runtime phases
+// 2-5 of the peformance-oriented language extensions, described below:
+//
+// PHASE 2: On program startup ("phase 2" function called from main()):
+// 1. Read the necessary ELF data associated with the executable image.
+// 2. For each function F (in section labelled ".text"), write code to call
+// phase 3.
+// 2a. Replace the first (replacable) instruction in F with a branch to a new
+// slot (annulling bit should specify *not* to execute the branch delay
+// slot) in the dummy function.
+// 2b. In the new slot, write the contents of the phase 3 slot (see
+// appropriate InstManip instance for detailed information about slot
+// contents).
+//
+// PHASE 3:
+// 0. Deallocate the parameter structure whenever it is convenient to do so.
+// 1. Replace the original (replaced) instruction at the proper location in the
+// original code.
+// 2. Analyze the function and determine the load-volatile candidates.
+// 3. For each load-volatile candidate,
+// 3a. Obtain a new slot in the dummy function.
+// 3b. Replace the load candidate with branch to slot.
+// 3c. In the new slot, write the contents of the phase 4 slot (see
+// appropriate InstManip instance for detailed information about slot
+// contents).
+// 4. Deallocate the slot that originated this invocation of phase3().
//
// PHASE 4:
-//
-// 1. Examine the tag (i.e. load-src addr) passed by phase 3
-// 1a. If tag is in GBT, we have a valid candidate, so do step 2.
-// 1b. If tag is not in GBT, our candidate is invalid, so restore original program state and
-// go to step 3.
-//
-// 2. Change the branch to the phase 4 slot to branch to a (new) phase 5 slot. See
-// appropriate InstManip instance for detailed information about phase 5 slot
-// contents. If there is no registered instrumentation for the phase 5 slot, leave a
-// nop in place of the branch to reduce runtime overhead.
-//
-// 3. Deallocate the slot that originated this invocation of phase4().
+// 1. Examine the tag (i.e. load-src addr) passed by phase 3:
+// 1a. If tag is in GBT, we have a valid candidate, so do step 2.
+// 1b. If tag is not in GBT, our candidate is invalid, so restore original
+// program state and go to step 3.
+// 2. Change the branch to the phase 4 slot to branch to a (new) phase 5
+// slot. See appropriate InstManip instance for detailed information about
+// phase 5 slot contents. If there is no registered instrumentation for the
+// phase 5 slot, leave a nop in place of the branch to reduce runtime
+// overhead.
+// 3. Deallocate the slot that originated this invocation of Phase 4.
//
// PHASE 5: Phase 5 isn't like the other phases; rather, it simply invokes all
-// registered instrumentation functions for a particular site.
+// registered instrumentation functions for a particular site.
+//
+//===----------------------------------------------------------------------===//
+#include "InstManip.h"
+#include "PhaseInfo.h"
+#include "SparcInstManip.h"
+#include "reopt/Inst/ElfReader.h"
+#include "reopt/MemoryManager.h"
+#include "reopt/TraceCache.h"
+#include "reopt/VirtualMem.h"
+#include "reopt/InstrUtils.h"
#include <cassert>
#include <algorithm>
#include <iomanip>
@@ -62,37 +68,32 @@
#include <vector>
#include <list>
-#include "reopt/Inst/ElfReader.h"
-#include "reopt/MemoryManager.h"
-#include "reopt/TraceCache.h"
-#include "reopt/VirtualMem.h"
-#include "reopt/InstrUtils.h"
-
-#include "InstManip.h"
-#include "PhaseInfo.h"
-#include "SparcInstManip.h"
-
using std::vector;
using std::cerr;
using std::endl;
-// The function generated at compile-time by the 'mkexcl' command line utility; the
-// command line utility must be run on any object/archive files containing symbols that
-// must be excluded, and the generated file compiled and linked in.
-void makeExcludedSymbolSet(std::set<std::string>& set);
+namespace llvm {
-// Description of GBT contents emitted by phase 1. The extern reference to the GBT will be
-// resolved at link-time, and will point to the GBT itself. The size of the GBT is
-// obtained in the same manner.
+/// The function generated at compile-time by the 'mkexcl' command line utility;
+/// the command line utility must be run on any object/archive files containing
+/// symbols that must be excluded, and the generated file compiled and linked
+/// in.
+///
+void makeExcludedSymbolSet(std::set<std::string>& set);
+/// Description of GBT contents emitted by phase 1. The extern reference to the
+/// GBT will be resolved at link-time, and will point to the GBT itself. The
+/// size of the GBT is obtained in the same manner.
+///
extern unsigned ppGBTSize;
extern GBTElem ppGBT[];
typedef std::pair<uint64_t, uint64_t> AddressRange;
-// Phase2 is the class that is responsible for effecting the core of the phase 2
-// transformation; the global function phase2() is simply an C-linkage interface.
-
+/// Phase2 is the class that is responsible for effecting the core of the phase
+/// 2 transformation; the global function phase2() is simply an C-linkage
+/// interface.
+///
class Phase2
{
public:
@@ -108,10 +109,10 @@
InstManip* m_pIM;
};
-// Phase3 is the class that is responsible for making the "phase 3" transformation; the
-// global function phase3() is responsible for constructing one Phase3 instance per
-// invocation and invoking transform on it.
-
+/// Phase3 is the class that is responsible for making the "phase 3"
+/// transformation; the global function phase3() is responsible for constructing
+/// one Phase3 instance per invocation and invoking transform on it.
+///
class Phase3
{
public:
@@ -130,10 +131,10 @@
InstManip* m_pIM;
};
-// Phase4 is the class that is responsible for making the "phase 4" transformation; the
-// global function phase4() is responsible for constructing one Phase4 instance per
-// invocation and invoking transform on it.
-
+/// Phase4 is the class that is responsible for making the "phase 4"
+/// transformation; the global function phase4() is responsible for constructing
+/// one Phase4 instance per invocation and invoking transform on it.
+///
class Phase4
{
public:
@@ -151,12 +152,13 @@
uint64_t m_tag; // Entry to look for in the GBT
};
-// InstFunctionInfo is the class used to represent information (e.g., address of return
-// value, pointer-to-instrumentation function) about particular registered instrumentation
-// functions. In the case of end-interval functions, the link 'm_pStart' is filled in to
-// refer to the InstFunctionInfo instance that contains information about the
-// corresponding start-interval function.
-
+/// InstFunctionInfo is the class used to represent information (e.g., address
+/// of return value, pointer-to-instrumentation function) about particular
+/// registered instrumentation functions. In the case of end-interval
+/// functions, the link 'm_pStart' is filled in to refer to the InstFunctionInfo
+/// instance that contains information about the corresponding start-interval
+/// function.
+///
class InstFunctionInfo
{
public:
@@ -187,12 +189,12 @@
bool m_invoked; // Has this function been invoked yet?
};
-// InstSiteInfo instances contain information about the state of particular
-// instrumentation sites. More specifically, it holds the instrumentation
-// status (e.g. whether or not the site has been handled by phase 4 yet) of the
-// sites as well as the list of (pointers to) the InstFunctionInfo instances
-// registered with a particular site.
-
+/// InstSiteInfo instances contain information about the state of particular
+/// instrumentation sites. More specifically, it holds the instrumentation
+/// status (e.g. whether or not the site has been handled by phase 4 yet) of the
+/// sites as well as the list of (pointers to) the InstFunctionInfo instances
+/// registered with a particular site.
+///
class InstSiteInfo
{
public:
@@ -202,19 +204,19 @@
{
}
- // For start-interval sites only -- allocates memory for the return value of
- // the instrumentation function (size of allocated memory is retValBytes).
- // Returns a pointer to the InstFunctionInfo* that corresponds to the
- // instrumentation function, or null if the function has already been
- // registered.
-
+ /// For start-interval sites only -- allocates memory for the return value
+ /// of the instrumentation function (size of allocated memory is
+ /// retValBytes). Returns a pointer to the InstFunctionInfo* that
+ /// corresponds to the instrumentation function, or null if the function has
+ /// already been registered.
+ ///
InstFunctionInfo* push_back(unsigned retValBytes,
void* func);
- // For end-interval sites (w/ optional link to corresponding start); other
- // site types should use this routine as well. The provided retVal ptr is
- // used as the return-value parameter of the instrumentation function.
-
+ /// For end-interval sites (w/ optional link to corresponding start); other
+ /// site types should use this routine as well. The provided retVal ptr is
+ /// used as the return-value parameter of the instrumentation function.
+ ///
void push_back(void* retVal,
void* func,
InstFunctionInfo* startInfo = 0);
@@ -222,12 +224,12 @@
void invokeFunctions();
protected:
- bool m_branchInstalled; // Installed branch to slot yet?
- bool m_instrumented; // Has phase 4 instrumented site?
- uint64_t m_brInstallAddr; // Address to install branch inst
- unsigned m_branchInst; // The branch inst to install
- std::set<void*> m_registeredFuncs; // Set of func-ptrs registered here
- vector<InstFunctionInfo*> m_instFuncInfos; // Info for all registered funcs
+ bool m_branchInstalled; // Installed branch to slot yet?
+ bool m_instrumented; // Has phase 4 instrumented site?
+ uint64_t m_brInstallAddr; // Address to install branch inst
+ unsigned m_branchInst; // The branch inst to install
+ std::set<void*> m_registeredFuncs; // Set of func-ptrs registered here
+ vector<InstFunctionInfo*> m_instFuncInfos; // Info for all registered funcs
friend void Phase4::transform();
@@ -247,18 +249,18 @@
}
};
-// InstInfo is the class that holds data about the instrumentation that gets
-// bound to instrumentation sites and intervals at runtime. There should only
-// be on instance of this class (i.e., it is a singleton class). The
-// implementation hides an STL map that maps the unique identifier associated
-// with an instrumentation interval/site to a pair of InstSiteInfo instances,
-// which contains the information about the instrumentations registered for the
-// given interval or point site. In the case of intervals, the first element of
-// the pair is the InstSiteInfo instance that contains data about the start
-// site, whereas the second element of the pair contains data about the end
-// site. For point sites, only the first element of the pair contains valid
-// data.
-
+/// InstInfo is the class that holds data about the instrumentation that gets
+/// bound to instrumentation sites and intervals at runtime. There should only
+/// be on instance of this class (i.e., it is a singleton class). The
+/// implementation hides an STL map that maps the unique identifier associated
+/// with an instrumentation interval/site to a pair of InstSiteInfo instances,
+/// which contains the information about the instrumentations registered for the
+/// given interval or point site. In the case of intervals, the first element
+/// of the pair is the InstSiteInfo instance that contains data about the start
+/// site, whereas the second element of the pair contains data about the end
+/// site. For point sites, only the first element of the pair contains valid
+/// data.
+///
class InstInfo
{
public:
@@ -312,7 +314,9 @@
InstInfo* InstInfo::m_pInstance = 0;
-//////////////// Phase 2 implementation ////////////////
+//===----------------------------------------------------------------------===//
+// Phase 2 Implementation
+//===----------------------------------------------------------------------===//
extern "C" void phase2()
{
@@ -381,7 +385,7 @@
vm->writeInstToVM(currAddr, *i);
currAddr += im->getInstWidth();
}
- ::doFlush(slotBase, slotBase + im->getInstWidth() * snippet.size());
+ doFlush(slotBase, slotBase + im->getInstWidth() * snippet.size());
}
static uint64_t makeNewSlot(uint64_t srcAddr,
@@ -408,7 +412,7 @@
// Replace instruction at srcAddr with branch to start of new slot
tc->getVM()->writeInstToVM(srcAddr, branchInst);
- ::doFlush(srcAddr, srcAddr + im->getInstWidth());
+ doFlush(srcAddr, srcAddr + im->getInstWidth());
return slotBase;
}
@@ -493,24 +497,25 @@
<< HEX(m_pPhase3Info->getRange().second)
<< "] ================\n");
- // 1. Replace the original (replaced) instruction at the proper location in the
- // original code (thus effectively removing the branch to the slot created by phase 2
- // as well).
+ // 1. Replace the original (replaced) instruction at the proper location in
+ // the original code (thus effectively removing the branch to the slot
+ // created by phase 2 as well).
m_pTC->getVM()->writeInstToVM(p3info->getReplaceAddr(), p3info->getOrigInst());
- ::doFlush(m_pPhase3Info->getReplaceAddr(),
- m_pPhase3Info->getReplaceAddr() + m_pIM->getInstWidth());
+ doFlush(m_pPhase3Info->getReplaceAddr(),
+ m_pPhase3Info->getReplaceAddr() + m_pIM->getInstWidth());
}
Phase3::~Phase3()
{
// Deallocate the originating slot (i.e. the slot that invoked us).
//
- // NB: Yes, we are, in fact, deallocating a memory segment (i.e., the slot obtained by
- // the TraceCache's MemoryManager instance) before returning to it. This is not a
- // problem for single-threaded codes, because no threads may claim that memory and
- // write to it. However, it does indeed pose a problem for multi-threaded codes. A
- // modification to the general mechanism itself is required to achieve thread-safety.
+ // NB: Yes, we are, in fact, deallocating a memory segment (i.e., the slot
+ // obtained by the TraceCache's MemoryManager instance) before returning to
+ // it. This is not a problem for single-threaded codes, because no threads
+ // may claim that memory and write to it. However, it does indeed pose a
+ // problem for multi-threaded codes. A modification to the general
+ // mechanism itself is required to achieve thread-safety.
uint64_t slotBase = m_pPhase3Info->getSlot();
unsigned slotSize = m_pPhase3Info->getSlotSize();
@@ -522,8 +527,8 @@
void Phase3::processCandidates(vector<InstCandidate>& candidates)
{
- // For each load candidate, obtain a new slot and write the phase 4 slot region
- // contents into it.
+ // For each load candidate, obtain a new slot and write the phase 4 slot
+ // region contents into it.
DEBUG_MSG(1, "There are " << candidates.size() << " candidates to process\n");
@@ -531,7 +536,8 @@
DEBUG_MSG(2, "Transforming " << candidates[i] << endl);
unsigned slotSize = m_pIM->getSlotSize(this, candidates[i]);
- // Replace load candidate instruction with a branch to the start of a new slot.
+ // Replace load candidate instruction with a branch to the start of a
+ // new slot.
uint64_t slotBase = replaceInstWithBrToSlot(candidates[i].front().first, slotSize,
m_pTC, m_pIM);
@@ -589,11 +595,12 @@
{
// Deallocate the originating slot (i.e. the slot that invoked us).
//
- // NB: Yes, we are, in fact, deallocating a memory segment (i.e., the slot obtained by
- // the TraceCache's MemoryManager instance) before returning to it. This is not a
- // problem for single-threaded codes, because no threads may claim that memory and
- // write to it. However, it does indeed pose a problem for multi-threaded codes. A
- // modification to the general mechanism itself is required to achieve thread-safety.
+ // NB: Yes, we are, in fact, deallocating a memory segment (i.e., the slot
+ // obtained by the TraceCache's MemoryManager instance) before returning to
+ // it. This is not a problem for single-threaded codes, because no threads
+ // may claim that memory and write to it. However, it does indeed pose a
+ // problem for multi-threaded codes. A modification to the general
+ // mechanism itself is required to achieve thread-safety.
uint64_t slotBase = m_pPhase4Info->getSlot();
unsigned slotSize = m_pPhase4Info->getSlotSize();
@@ -639,8 +646,8 @@
assert(cand.getInsts().size() >= 2
&& "Unexpected number of instructions in candidate");
- // Write NOPs over the original instructions that were associated with the elected
- // candidate.
+ // Write NOPs over the original instructions that were associated with
+ // the elected candidate.
VirtualMem* vm = m_pTC->getVM();
for(vector<std::pair<uint64_t, unsigned> >::const_iterator i = cand.getInsts().begin(),
@@ -681,9 +688,9 @@
}
else {
DEBUG_MSG(1, "does not match\n");
- // The candidate failed to get elected, so pack up and go home. Restore the
- // replaced instruction (i.e. the branch that invoked this code) with the original
- // instruction at that location.
+ // The candidate failed to get elected, so pack up and go home. Restore
+ // the replaced instruction (i.e. the branch that invoked this code)
+ // with the original instruction at that location.
VirtualMem* vm = m_pPhase4Info->getTraceCache()->getVM();
vm->writeInstToVM(m_pPhase4Info->getCandidate().front().first,
@@ -771,13 +778,14 @@
void InstFunctionInfo::invoke()
{
- // In the case of start-interval functions, the boolean m_invoked is set to true upon
- // completion of the invocation. This same boolean (i.e, the one associated with the
- // start-interval InstFunctionInfo instance) is cleared by the corresponding
- // end-interval function invocation. This is to ensure that no end-interval
- // instrumentation function is ever invoked unless its corresponding start-interval
- // instrumentation function has been invoked (which implies that the start-interval
- // site has been handled properly and all of the registration mechanisms).
+ // In the case of start-interval functions, the boolean m_invoked is set to
+ // true upon completion of the invocation. This same boolean (i.e, the one
+ // associated with the start-interval InstFunctionInfo instance) is cleared
+ // by the corresponding end-interval function invocation. This is to ensure
+ // that no end-interval instrumentation function is ever invoked unless its
+ // corresponding start-interval instrumentation function has been invoked
+ // (which implies that the start-interval site has been handled properly and
+ // all of the registration mechanisms).
DEBUG_MSG(3, "(InstFunctionInfo::invoke) retVal address is: " << HEX(m_pRetVal) << endl);
if(m_pStart) {
@@ -825,3 +833,5 @@
else
DEBUG_MSG(3, "WARNING: Register-start-function returned 0, which implies redundant registration");
}
+
+}; // end namespace llvm
Index: reopt/lib/Inst/lib/SparcInstManip.cpp
diff -u reopt/lib/Inst/lib/SparcInstManip.cpp:1.21 reopt/lib/Inst/lib/SparcInstManip.cpp:1.22
--- reopt/lib/Inst/lib/SparcInstManip.cpp:1.21 Fri Oct 10 13:45:30 2003
+++ reopt/lib/Inst/lib/SparcInstManip.cpp Wed Nov 19 14:49:53 2003
@@ -1,14 +1,22 @@
-////////////////
-// programmer: Joel Stanley
-// date: Tue Apr 29 21:21:50 CDT 2003
-// fileid: SparcInstManip.cpp
-// purpose: Implements the SparcInstManip class as described in SparcInstManip.h
-//
-// SparcInstManip implements behavior that constructs the contents of "slots" -- regions
-// of memory allocated by a MemoryManager instance and/or off of the heap that will be
-// branched to at runtime. A phase n slot is written by phase n-1, and is when executed,
-// invokes the appropriate function for phase n. The notable exception is the last phase,
-// which will end up invoking the proper instrumentation function.
+//===- SparcInstManip.cpp - SparcInstManip class implementation -----------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Originally written by Joel Stanley on 29-Apr-2003. Implements the
+// SparcInstManip class as described in SparcInstManip.h. SparcInstManip
+// implements behavior that constructs the contents of "slots" -- regions of
+// memory allocated by a MemoryManager instance and/or off of the heap that will
+// be branched to at runtime. A phase n slot is written by phase n-1, and is
+// when executed, invokes the appropriate function for phase n. The notable
+// exception is the last phase, which will end up invoking the proper
+// instrumentation function.
+//
+//===----------------------------------------------------------------------===//
//
// Phase 3 slot:
// +------------------------------------+
@@ -56,7 +64,8 @@
// | return to phase 5 jump slot |
// | nop |
// +-------------------------------------------------+
-// []
+//
+//===----------------------------------------------------------------------===//
#include "reopt/TraceCache.h"
#include "reopt/VirtualMem.h"
@@ -74,7 +83,10 @@
#include <cerrno>
#include <unistd.h> // valloc()
-// These are exported due to some inline methods in SparcInstManip.h
+using namespace llvm;
+
+/// These are exported due to some inline methods in SparcInstManip.h
+///
uint64_t SparcInstManip::sm_phase4SpillRegion[SparcInstManip::SHARED_SIZE];
const unsigned SparcInstManip::BRANCH_ALWAYS_BASE = 0x10480000;
const unsigned SparcInstManip::BRANCH_ALWAYS_BASE_ANNUL = 0x30480000;
Index: reopt/lib/Inst/lib/SparcInstManip.h
diff -u reopt/lib/Inst/lib/SparcInstManip.h:1.16 reopt/lib/Inst/lib/SparcInstManip.h:1.17
--- reopt/lib/Inst/lib/SparcInstManip.h:1.16 Fri Aug 22 12:43:40 2003
+++ reopt/lib/Inst/lib/SparcInstManip.h Wed Nov 19 14:49:53 2003
@@ -1,21 +1,28 @@
-////////////////
-// programmer: Joel Stanley
-// date: Tue Apr 29 21:17:33 CDT 2003
-// fileid: SparcInstManip.h
-// purpose: Provides description SparcV9-specifc InstManip class. In particular,
-// SparcInstManip wraps the BinInterface/TraceCache macros and utilities.
+//===- SparcInstManip.h - Wrappers for BinInterface/TraceCache --*- C++ -*-===//
+//
+// The LLVM Compiler Infrastructure
//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Originally written by Joel Stanley on 29-Apr-2003. Provides
+// SparcV9-specific InstManip class. In particular, SparcInstManip wraps the
+// BinInterface/TraceCache macros and utilities.
+//
+//===----------------------------------------------------------------------===//
-#ifndef _INCLUDED_SPARCINSTMANIP_H
-#define _INCLUDED_SPARCINSTMANIP_H
+#ifndef SPARCINSTMANIP_H
+#define SPARCINSTMANIP_H
#include "reopt/BinInterface/sparcdis.h"
#include "reopt/InstrUtils.h" // getCallInstr, getUndepJumpInstr, etc.
-
#include "InstManip.h"
-
#include <map>
+namespace llvm {
+
class SparcInstManip : public InstManip
{
public:
@@ -41,7 +48,8 @@
std::vector<InstCandidate>& candidates);
virtual uint64_t getStartAddr(uint64_t funcStartAddr) const;
- inline unsigned getBranchAlways(uint64_t dest, uint64_t pc, bool annulHigh = true) const;
+ inline unsigned getBranchAlways(uint64_t dest, uint64_t pc,
+ bool annulHigh = true) const;
inline bool isBranch(unsigned inst) const;
virtual void printRange(unsigned* start, unsigned* end) const;
virtual void printInst(unsigned inst) const;
@@ -57,8 +65,10 @@
unsigned getPhase5HeapSize() const;
- void startCode(std::vector<unsigned>& snippet) { m_pCurrSnippet = &snippet; }
- void endCode() { m_pCurrSnippet = 0; }
+ void startCode(std::vector<unsigned>& snippet) {
+ m_pCurrSnippet = &snippet;
+ }
+ void endCode() { m_pCurrSnippet = 0; }
void generateAddressCopy(unsigned loadInst,
LogicalRegister dest,
@@ -85,8 +95,10 @@
LogicalRegister dest,
LogicalRegister tmp);
- void generateStackStore(LogicalRegister src, unsigned stkOffset);
- void generateStackLoad(LogicalRegister dest, unsigned stkOffset);
+ void generateStackStore(LogicalRegister src,
+ unsigned stkOffset);
+ void generateStackLoad(LogicalRegister dest,
+ unsigned stkOffset);
void generateRestore();
void generateSave(unsigned offset = STKFRM_MIN);
@@ -128,30 +140,37 @@
unsigned align = STACK_ALIGN);
std::vector<unsigned>* m_pCurrSnippet;
- GBTStackMap m_gbtStackMap; // Maps GBTElem* -> param address stack
- OutputToInputRegMap m_outputToInputReg; // Maps input register -> output register
+ // Maps GBTElem* -> param address stack
+ GBTStackMap m_gbtStackMap;
+ // Maps input register -> output register
+ OutputToInputRegMap m_outputToInputReg;
// Size (in number of 64-bit words) required for storing shared registers
+ //
static const unsigned SHARED_SIZE = 7;
- // The memory region into which to spill shared registers when executing a phase 4
- // slot (i.e., the slot that invokes the phase4 function, the slot written by phase 3
- // invocations). NB: One region is sufficient and we do not need stack semantics
- // because only one activation of a phase 4 slot ever occurs at a given time (assuming
- // single-threaded execution).
-
+ // The memory region into which to spill shared registers when executing a
+ // phase 4 slot (i.e., the slot that invokes the phase4 function, the slot
+ // written by phase 3 invocations). NB: One region is sufficient and we do
+ // not need stack semantics because only one activation of a phase 4 slot
+ // ever occurs at a given time (assuming single-threaded execution).
+ //
static uint64_t sm_phase4SpillRegion[SHARED_SIZE];
- // Branch-always (annul bit high) instruction base (address not filled in yet)
+ // Branch-always (annul bit high) instruction base (address not filled in
+ // yet)
+ //
static const unsigned BRANCH_ALWAYS_BASE_ANNUL;
- // Branch-always (annul bit low) instruction base (address not filled in yet)
+ // Branch-always (annul bit low) instruction base (address not filled in
+ // yet)
+ //
static const unsigned BRANCH_ALWAYS_BASE;
static const unsigned INST_WIDTH = 4; // In bytes
static const unsigned NOP_INST = 0x01000000;
static const unsigned BIAS = 2047;
- static const unsigned STKFRM_MIN = 176; // Smallest allowable stack frm size
+ static const unsigned STKFRM_MIN = 176; // Smallest allowed stack frm size
static const unsigned STACK_ALIGN = 16;
static const unsigned SEARCH_DELTA = 20;
static const unsigned WORD_WIDTH = 8;
@@ -167,51 +186,58 @@
static const unsigned GEN_STKSTORE_SIZE = 1;
static const unsigned GEN_STKLOAD_SIZE = 1;
static const unsigned GEN_RESTORE_SIZE = 1;
- static const unsigned GEN_SPL_SIZE = GEN_LOAD_SIZE + SHARED_SIZE;
- static const unsigned GEN_SPL_STK_SIZE = SHARED_SIZE;
- static const unsigned GEN_UNSPL_SIZE = GEN_SPL_SIZE;
- static const unsigned GEN_UNSPL_STK_SIZE = GEN_SPL_STK_SIZE;
- static const unsigned GEN_SPSUB_SIZE = 1;
- static const unsigned GEN_SPOFFSET_SIZE = 1;
- static const unsigned GEN_JMPL_SIZE = 2;
- static const unsigned GEN_LDJMPL_SIZE = GEN_LOAD_SIZE + GEN_JMPL_SIZE;
- static const unsigned GEN_MOV_SIZE = 1;
+ static const unsigned GEN_SPL_SIZE = GEN_LOAD_SIZE + SHARED_SIZE;
+ static const unsigned GEN_SPL_STK_SIZE = SHARED_SIZE;
+ static const unsigned GEN_UNSPL_SIZE = GEN_SPL_SIZE;
+ static const unsigned GEN_UNSPL_STK_SIZE = GEN_SPL_STK_SIZE;
+ static const unsigned GEN_SPSUB_SIZE = 1;
+ static const unsigned GEN_SPOFFSET_SIZE = 1;
+ static const unsigned GEN_JMPL_SIZE = 2;
+ static const unsigned GEN_LDJMPL_SIZE = GEN_LOAD_SIZE + GEN_JMPL_SIZE;
+ static const unsigned GEN_MOV_SIZE = 1;
};
-unsigned SparcInstManip::getBranchAlways(uint64_t dest, uint64_t pc, bool annul) const
+/// Return a branch always instruction. dest is the destination address, pc is
+/// the value of the program counter when the branch instruction is executed
+/// (i.e., the address of the branch instruction). NB: Only handles
+/// branch-always-annul-high at the moment.
+///
+unsigned SparcInstManip::getBranchAlways(uint64_t dest, uint64_t pc,
+ bool annul) const
{
- // dest is the destination address, pc is the value of the program counter when the
- // branch instruction is executed (i.e., the address of the branch instruction). NB:
- // Only handles branch-always-annul-high at the moment
-
- return getUndepJumpInstr(annul ? BRANCH_ALWAYS_BASE_ANNUL : BRANCH_ALWAYS_BASE,
- dest,
- pc);
+ return
+ getUndepJumpInstr(annul ? BRANCH_ALWAYS_BASE_ANNUL : BRANCH_ALWAYS_BASE,
+ dest, pc);
}
+/// Returns a call instruction. dest is the destination address to call, pc is
+/// the value of the program counter when the call instruction is executed
+/// (i.e., the address of the branch instruction).
+///
unsigned SparcInstManip::getCallInst(uint64_t dest, uint64_t pc) const
{
- // dest is the destination address to call, pc is the value of the program counter
- // when the call instruction is executed (i.e., the address of the branch
- // instruction).
-
return getCallInstr(dest, pc);
}
+/// Returns true IFF inst is a branch instruction.
+///
bool SparcInstManip::isBranch(unsigned inst) const
{
- return ::isBranchInstr(inst);
+ return isBranchInstr(inst);
}
+/// Determine the number of instructions required to load the address value used
+/// by the load instruction into some register.
+///
unsigned SparcInstManip::getGenAddressCopySize(unsigned loadInst) const
{
- // Determine the number of instructions required to load the address value used by the
- // load instruction into some register.
-
- // Case 1: load is immediate-valued --> add-immediate instruction needed, size is 1 inst
- // Case 2: load is register-valued --> add-registers instruction needed, size is 1 inst
-
+ // Case 1: load is immediate-valued --> add-immediate instruction needed,
+ // size is 1 inst.
+ // Case 2: load is register-valued --> add-registers instruction needed,
+ // size is 1 inst.
return 1;
}
-#endif // _INCLUDED_SPARCINSTMANIP_H
+} // end namespace llvm
+
+#endif // SPARCINSTMANIP_H
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