[llvm-commits] CVS: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp
Brian Gaeke
gaeke at cs.uiuc.edu
Sat Nov 8 23:31:00 PST 2003
Changes in directory reopt/lib/LightWtProfiling:
UnpackTraceFunction.cpp updated: 1.18 -> 1.19
---
Log message:
Get rid of 31337 SrcReg and TargReg variables in insertCopyMachineInstrs().
Call TargetRegInfo::getUnifiedRegNum() by its proper name.
Update insertBranchMachineInstrs() to use some 31337 code that I am ready to
commit to SparcV9CodeEmitter once all the Bug 103 poop has stopped flying.
---
Diffs of the changes: (+19 -67)
Index: reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp
diff -u reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.18 reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.19
--- reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp:1.18 Sat Nov 8 13:08:33 2003
+++ reopt/lib/LightWtProfiling/UnpackTraceFunction.cpp Sat Nov 8 23:30:26 2003
@@ -1,6 +1,5 @@
//===- UnpackTraceFunction.cpp - Convert functions back to traces -*- C++ -*-=//
//
-// WARNING, WARNING, WARNING; THIS IS HALF-UNIMPLEMENTED WORK IN PROGRESS!
// Methods to convert functions, which had previously been converted from
// traces into functions, back into traces.
//
@@ -28,7 +27,6 @@
UltraSparc TM;
const TargetRegInfo &TRI = TM.getRegInfo ();
std::vector<MachineInstr *> mvec;
- unsigned SrcReg = 31337, TargReg = 31337;
int RegType;
// Guess what kind of reg the register was allocated to.
if (Ty == Type::FloatTy)
@@ -37,16 +35,13 @@
RegType = UltraSparcRegInfo::FPDoubleRegType;
else
RegType = UltraSparcRegInfo::IntRegType;
- if (Source.AllocState == AllocInfo::Allocated)
- SrcReg = Source.Placement;
- if (Target.AllocState == AllocInfo::Allocated)
- TargReg = Target.Placement;
const unsigned FramePtrReg = TRI.getFramePointer ();
const unsigned StackPtrReg = TRI.getStackPointer ();
if (Source.AllocState == AllocInfo::Spilled
&& Target.AllocState == AllocInfo::Allocated) {
// Emit load instruction from stack loc. Source into register Target
- TRI.cpMem2RegMI (mvec, FramePtrReg, Source.Placement, TargReg, RegType);
+ TRI.cpMem2RegMI (mvec, FramePtrReg, Source.Placement, Target.Placement,
+ RegType);
} else if (Source.AllocState == AllocInfo::Allocated
&& Target.AllocState == AllocInfo::Allocated) {
// Emit move instruction from register Source to register Target
@@ -59,8 +54,8 @@
} else if (Source.AllocState == AllocInfo::Spilled
&& Target.AllocState == AllocInfo::Spilled) {
const unsigned TempReg =
- getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
- SparcIntRegClass::g1); // just pick one?
+ TRI.getUnifiedRegNum (UltraSparcRegInfo::IntRegClassID,
+ SparcIntRegClass::g1); // just pick one?
// Emit load instruction from stack loc. Source into register TempReg
TRI.cpMem2RegMI (mvec, FramePtrReg, Source.Placement, TempReg, RegType);
// Emit store instruction from register TempReg to stack loc. Target
@@ -73,66 +68,23 @@
B.push_back (*i);
}
-/// Emit the same sequence of MachineInstrs that
-/// replaceMachineCodeForFunction() would emit, to branch from the end
-/// of B to TargetAddr. Note that the current implementation is
-/// SPARC-specific.
-///
-/// FIXME: refactor this so it shares code with SparcV9CodeEmitter.cpp's
-/// JITResolver::insertJumpAtAddr(), JITResolver::insertFarJumpAtAddr()
+/// Emit a branch from the end of B to TargetAddr. Note that the current
+/// implementation is SPARC-specific.
///
void insertBranchMachineInstrs (uint64_t Target, MachineBasicBlock &B) {
- DEBUG(std::cerr << "Emitting a jump to 0x" << std::hex << Target << "\n");
-
- // FIXME: A "near jump" (Branch Always instruction) will get the
- // WRONG address by this method, because the binary value of the
- // instruction depends on the exact displacement from the branch
- // source. Near jumps are disabled for now.
- const int64_t Addr = (int64_t)(intptr_t)dummyFunction2;
-
- int64_t BranchTarget = (Target-Addr) >> 2;
- if (1 || (BranchTarget >= (1 << 19) || BranchTarget <= -(1 << 19))) {
- /// FAR JUMP
- static const unsigned
- o6 = SparcIntRegClass::o6, g0 = SparcIntRegClass::g0,
- g1 = SparcIntRegClass::g1, g5 = SparcIntRegClass::g5;
-
- MachineInstr* BinaryCode[] = {
- // Get address to branch into %g1, using %g5 as a temporary
- //
- // sethi %uhi(Target), %g5 ;; get upper 22 bits of Target into %g5
- BuildMI(V9::SETHI, 2).addSImm(Target >> 42).addReg(g5),
- // or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %g5
- BuildMI(V9::ORi,3).addReg(g5).addSImm((Target >> 32) & 0x03ff).addReg(g5),
- // sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
- BuildMI(V9::SLLXi6, 3).addReg(g5).addSImm(32).addReg(g5),
- // sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
- BuildMI(V9::SETHI, 2).addSImm((Target >> 10) & 0x03fffff).addReg(g1),
- // or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
- BuildMI(V9::ORr, 3).addReg(g5).addReg(g1).addReg(g1),
- // or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
- BuildMI(V9::ORi, 3).addReg(g1).addSImm(Target & 0x03ff).addReg(g1),
- // jmpl %g1, %g0, %g0 ;; indirect branch on %g1
- BuildMI(V9::JMPLRETr, 3).addReg(g1).addReg(g0).addReg(g0),
- // nop ;; delay slot
- BuildMI(V9::NOP, 0)
- };
-
- for (unsigned i=0, e=sizeof(BinaryCode)/sizeof(BinaryCode[0]); i!=e; ++i)
- B.push_back (BinaryCode[i]);
- } else {
- /// NEAR JUMP: use "ba" instruction
- // If the target function is close enough to fit into the 19bit disp of
- // BA, we should use this version, as it's much cheaper to generate.
-
- // ba <target>
- MachineInstr *I = BuildMI(V9::BA, 1).addSImm(BranchTarget);
- B.push_back (I);
-
- // nop
- I = BuildMI(V9::NOP, 0);
- B.push_back (I);
- }
+ // If the target is close enough to fit into the 19-bit disp of a "ba"
+ // instruction, then we really DO get a "ba" instruction. We get the backend
+ // to calculate the PC-relative address from the absolute address upon
+ // emitting it to memory, by handing it a Constant and telling the backend
+ // it's a PC-relative MachineOperand. If the target is NOT close enough to
+ // fit in a "ba" instruction, the SparcV9CodeEmitter will automatically turn
+ // it into an indirect jump through a register.
+
+ // ba <target>
+ Constant *TargetAsConstant = (ConstantUInt::get (Type::ULongTy, Target));
+ B.push_back (BuildMI (V9::BA, 1).addPCDisp (TargetAsConstant));
+ // nop
+ B.push_back (BuildMI (V9::NOP, 0));
}
extern "C" {
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