[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegInfo.cpp SparcV9_Reg.td

[Brian Gaeke]

Changes in directory llvm/lib/Target/Sparc:

SparcRegInfo.cpp updated: 1.112 -> 1.113
SparcV9_Reg.td updated: 1.6 -> 1.7

---
Log message:

Fix two typos I found in comments.


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Diffs of the changes:  (+3 -3)

Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.112 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.113
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.112	Mon Oct 20 14:43:17 2003
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp	Sat Nov  8 12:12:24 2003
@@ -760,7 +760,7 @@
       RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
       OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
 #else
-      // Default to using register g2 for holding large offsets
+      // Default to using register g4 for holding large offsets
       OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
                                 SparcIntRegClass::g4);
 #endif
@@ -845,7 +845,7 @@
       RegClass* RC = PRA.getRegClassByID(this->getRegClassIDOfRegType(RegType));
       OffReg = PRA.getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
 #else
-      // Default to using register g2 for holding large offsets
+      // Default to using register g4 for holding large offsets
       OffReg = getUnifiedRegNum(UltraSparcRegInfo::IntRegClassID,
                                 SparcIntRegClass::g4);
 #endif


Index: llvm/lib/Target/Sparc/SparcV9_Reg.td
diff -u llvm/lib/Target/Sparc/SparcV9_Reg.td:1.6 llvm/lib/Target/Sparc/SparcV9_Reg.td:1.7
--- llvm/lib/Target/Sparc/SparcV9_Reg.td:1.6	Tue Oct 21 10:17:13 2003
+++ llvm/lib/Target/Sparc/SparcV9_Reg.td	Sat Nov  8 12:12:24 2003
@@ -32,7 +32,7 @@
 
 // For fun, specify a register class.
 //
-// FIXME: the register order should be defined in terms of the prefered
+// FIXME: the register order should be defined in terms of the preferred
 // allocation order...
 //
 def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,