[llvm-commits] [regalloc_linearscan] CVS: llvm/lib/CodeGen/RegAllocLinearScan.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Thu Nov 6 03:48:01 PST 2003
Changes in directory llvm/lib/CodeGen:
RegAllocLinearScan.cpp updated: 1.1.2.7 -> 1.1.2.8
---
Log message:
Reached a state where assignments for virtual => physical registers
are computed. No operands are computed and no already physical
register allocations are considered.
---
Diffs of the changes: (+38 -10)
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.1.2.7 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.1.2.8
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.1.2.7 Wed Nov 5 20:25:37 2003
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Thu Nov 6 03:47:43 2003
@@ -37,7 +37,6 @@
private:
MachineFunction* mf_;
const TargetMachine* tm_;
- const TargetRegInfo* tri_;
const MRegisterInfo* mri_;
MachineBasicBlock* currentMbb_;
MachineBasicBlock::iterator currentInstr_;
@@ -137,29 +136,43 @@
}
bool RA::runOnMachineFunction(MachineFunction &fn) {
- DEBUG(std::cerr << "Machine Function\n");
mf_ = &fn;
tm_ = &fn.getTarget();
- tri_ = &tm_->getRegInfo();
mri_ = tm_->getRegisterInfo();
li_ = &getAnalysis<LiveIntervals>().getIntervals();
active_.clear();
inactive_.clear();
mii2mbbMap_ = &getAnalysis<LiveIntervals>().getMiIndex2MbbMap();
mbb2miiMap_ = &getAnalysis<LiveIntervals>().getMbb2MiIndexMap();
+ p2vMap_.resize(MRegisterInfo::FirstVirtualRegister-1);
p2vMap_.clear();
v2pMap_.clear();
v2ssMap_.clear();
instrAdded_ = 0;
// liner scan algorithm
-
+ DEBUG(std::cerr << "Processing " << li_->size() << " instervals\n");
for (Intervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
- unsigned curInstrIndex = i->start();
- tie(currentMbb_, currentInstr_) = getMbbMbbIteratorPair(curInstrIndex);
+ tie(currentMbb_, currentInstr_) = getMbbMbbIteratorPair(i->start());
+ DEBUG(std::cerr << "instruction[" << i->start() << "]: "
+ << **currentInstr_);
assert(currentInstr_ >= currentMbb_->begin() &&
currentInstr_ < currentMbb_->end() &&
"current instruction/machine basic block mismatch");
+ DEBUG(
+ std::cerr << "active intervals:\n";
+ for (IntervalPtrs::const_iterator
+ i = active_.begin(), e = active_.end(); i != e; ++i) {
+ std::cerr << '\t' << **i << '\n';
+ }
+ std::cerr << "inactive intervals:\n";
+ for (IntervalPtrs::const_iterator
+ i = inactive_.begin(), e = inactive_.end(); i != e; ++i) {
+ std::cerr << '\t' << **i << '\n';
+ }
+ );
+
+
processActiveIntervals(i);
processInactiveIntervals(i);
@@ -177,17 +190,19 @@
void RA::processActiveIntervals(Intervals::iterator cur)
{
+ DEBUG(std::cerr << "\tprocessing active intervals:\n");
unsigned curInstrIndex = cur->start();
- for (IntervalPtrs::iterator
- i = active_.begin(), e = active_.end(); i != e;) {
+ for (IntervalPtrs::iterator i = active_.begin(); i != active_.end();) {
unsigned virtReg = (*i)->reg;
// remove expired intervals
if ((*i)->expired(curInstrIndex)) {
+ DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
freeReg(virtReg);
// remove interval from active
i = active_.erase(i);
}
else if (!(*i)->overlaps(curInstrIndex)) {
+ DEBUG(std::cerr << "\t\tinterval " << **i << " inactive\n");
unmarkReg(virtReg);
// add interval to inactive
inactive_.push_back(*i);
@@ -202,16 +217,18 @@
void RA::processInactiveIntervals(Intervals::iterator cur)
{
+ DEBUG(std::cerr << "\tprocessing inactive intervals:\n");
unsigned curInstrIndex = cur->start();
- for (IntervalPtrs::iterator
- i = inactive_.begin(), e = inactive_.end(); i != e;) {
+ for (IntervalPtrs::iterator i = inactive_.begin(); i != inactive_.end();) {
unsigned virtReg = (*i)->reg;
if ((*i)->expired(curInstrIndex)) {
+ DEBUG(std::cerr << "\t\tinterval " << **i << " expired\n");
freeReg(virtReg);
// remove from inactive
i = inactive_.erase(i);
}
else if ((*i)->overlaps(curInstrIndex)) {
+ DEBUG(std::cerr << "\t\tinterval " << **i << " active\n");
markReg(virtReg);
// add to active
active_.push_back(*i);
@@ -226,6 +243,7 @@
void RA::spillAtInterval(Intervals::iterator cur)
{
+ DEBUG(std::cerr << "\tspilling at interval " << *cur << ":\n");
assert(!active_.empty() &&
"active set cannot be empty when choosing a register to spill");
IntervalPtrs::iterator lastEnd = active_.begin();
@@ -244,9 +262,16 @@
}
}
+ DEBUG(std::cerr << "\t\tspilling interval " << **lastEnd << "\n");
// spill last in active and inactive
spillVirtReg((*lastEnd)->reg);
freeReg((*lastEnd)->reg);
+ if (inInactive) {
+ inactive_.erase(lastEnd);
+ }
+ else {
+ active_.erase(lastEnd);
+ }
}
bool RA::physRegAvailable(unsigned physReg)
@@ -267,6 +292,7 @@
unsigned RA::getFreeReg(unsigned virtReg)
{
+ DEBUG(std::cerr << "\tgetting free register: ");
const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(virtReg);
TargetRegisterClass::iterator reg = rc->allocation_order_begin(*mf_);
TargetRegisterClass::iterator regEnd = rc->allocation_order_end(*mf_);
@@ -274,10 +300,12 @@
for (; reg != regEnd; ++reg) {
if (physRegAvailable(*reg)) {
assert(*reg != 0 && "Cannot use register!");
+ DEBUG(std::cerr << mri_->getName(*reg) << '\n');
return *reg; // Found an unused register!
}
}
+ DEBUG(std::cerr << "no free register\n");
return 0;
}
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