[llvm-commits] [regalloc_linearscan] CVS: llvm/include/llvm/CodeGen/LiveIntervals.h

[Alkis Evlogimenos]

Changes in directory llvm/include/llvm/CodeGen:

LiveIntervals.h added (r1.1.2.1)

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Log message:

Add live interval analysis pass

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Diffs of the changes:  (+95 -0)

Index: llvm/include/llvm/CodeGen/LiveIntervals.h
diff -c /dev/null llvm/include/llvm/CodeGen/LiveIntervals.h:1.1.2.1
*** /dev/null	Fri Oct 24 01:06:57 2003
--- llvm/include/llvm/CodeGen/LiveIntervals.h	Fri Oct 24 01:06:46 2003
***************
*** 0 ****
--- 1,95 ----
+ //===-- llvm/CodeGen/LiveInterval.h - Live Interval Analysis ---*- C++ -*-===//
+ // 
+ // This file implements the LiveInterval analysis pass.  Given some
+ // numbering of each the machine instructions (in this implemenation
+ // depth-first order) an interval [i, j] is said to be a live interval
+ // for register v if there is no instruction with number j' > j such
+ // that v is live at j' abd there is no instruction with number i' < i
+ // such that v is live at i'.
+ //   
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef LLVM_CODEGEN_LIVEINTERVALS_H
+ #define LLVM_CODEGEN_LIVEINTERVALS_H
+ 
+ #include "llvm/CodeGen/MachineFunctionPass.h"
+ #include "llvm/CodeGen/MachineBasicBlock.h"
+ #include <map>
+ 
+ class LiveVariables;
+ class MRegisterInfo;
+ 
+ class LiveIntervals : public MachineFunctionPass {
+ public:
+     struct Interval {
+         unsigned reg;   // the register of this interval
+         unsigned start; // the start instruction (def)
+         unsigned end;   // the end instruction (last use)
+ 
+         Interval(unsigned r, unsigned b, unsigned e)
+             : reg(r), start(b), end(e) {
+ 
+         }
+     };
+ 
+     struct StartPointComp {
+         bool operator()(const Interval& lhs, const Interval& rhs) {
+             return lhs.start < rhs.start;
+         }
+     };
+ 
+     struct EndPointComp {
+         bool operator()(const Interval& lhs, const Interval& rhs) {
+             return lhs.end < rhs.end;
+         }
+     };
+ 
+ private:
+     MachineFunction* _mf;
+     const TargetMachine* _tm;
+     const MRegisterInfo* _mri;
+     MachineBasicBlock* _currentMbb;
+     MachineBasicBlock::iterator _currentInstr;
+     LiveVariables* _lv;
+     
+     typedef std::vector<MachineBasicBlock*> MBBPtrs;
+     MBBPtrs _mbbOrder;
+ 
+     typedef std::map<MachineInstr*, unsigned> Instr2IndexMap;
+     Instr2IndexMap _i2iMap;
+ 
+     typedef std::vector<Interval> Intervals;
+     Intervals _intervals;
+ 
+     typedef std::map<unsigned, unsigned> Reg2IntervalMap;
+ 
+ public:
+     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
+ 
+ private:
+     /// runOnMachineFunction - pass entry point
+     bool runOnMachineFunction(MachineFunction&);
+ 
+     /// computeIntervals - compute live intervals
+     void computeIntervals();
+ 
+     /// handleRegisterDef - update intervals for a register def
+     void handleRegisterDef(Reg2IntervalMap& r2iMap, unsigned i, unsigned reg);
+ 
+     /// handleRegisterKill - update intervals for a register kill
+     void handleRegisterKill(Reg2IntervalMap& r2iMap, unsigned i, unsigned reg);
+ };
+ 
+ inline bool operator==(const LiveIntervals::Interval& lhs,
+                        const LiveIntervals::Interval& rhs) {
+     return lhs.reg == rhs.reg;
+ }
+ 
+ inline std::ostream& operator<<(std::ostream& os,
+                                 const LiveIntervals::Interval& i) {
+     return os << "[ %reg" << i.reg << ", "
+               << i.start << ", " << i.end << "]";
+ }
+ 
+ 
+ #endif