[llvm-commits] CVS: llvm/lib/Transforms/Scalar/LICM.cpp Mem2Reg.cpp ScalarReplAggregates.cpp

[Chris Lattner]

Changes in directory llvm/lib/Transforms/Scalar:

LICM.cpp updated: 1.34 -> 1.35
Mem2Reg.cpp updated: 1.5 -> 1.6
ScalarReplAggregates.cpp updated: 1.14 -> 1.15

---
Log message:

Change the interface to PromoteMemToReg to also take a DominatorTree


---
Diffs of the changes:

Index: llvm/lib/Transforms/Scalar/LICM.cpp
diff -u llvm/lib/Transforms/Scalar/LICM.cpp:1.34 llvm/lib/Transforms/Scalar/LICM.cpp:1.35
--- llvm/lib/Transforms/Scalar/LICM.cpp:1.34	Thu Sep 11 11:26:10 2003
+++ llvm/lib/Transforms/Scalar/LICM.cpp	Sun Oct  5 16:20:02 2003
@@ -63,6 +63,7 @@
   private:
     LoopInfo      *LI;       // Current LoopInfo
     AliasAnalysis *AA;       // Current AliasAnalysis information
+    DominanceFrontier *DF;   // Current Dominance Frontier
     bool Changed;            // Set to true when we change anything.
     BasicBlock *Preheader;   // The preheader block of the current loop...
     Loop *CurLoop;           // The current loop we are working on...
@@ -173,6 +174,7 @@
   // Get our Loop and Alias Analysis information...
   LI = &getAnalysis<LoopInfo>();
   AA = &getAnalysis<AliasAnalysis>();
+  DF = &getAnalysis<DominanceFrontier>();
   DT = &getAnalysis<DominatorTree>();
 
   // Hoist expressions out of all of the top-level loops.
@@ -405,8 +407,7 @@
   PromotedAllocas.reserve(PromotedValues.size());
   for (unsigned i = 0, e = PromotedValues.size(); i != e; ++i)
     PromotedAllocas.push_back(PromotedValues[i].first);
-  PromoteMemToReg(PromotedAllocas, getAnalysis<DominanceFrontier>(),
-                  AA->getTargetData());
+  PromoteMemToReg(PromotedAllocas, *DT, *DF, AA->getTargetData());
 }
 
 /// findPromotableValuesInLoop - Check the current loop for stores to definite


Index: llvm/lib/Transforms/Scalar/Mem2Reg.cpp
diff -u llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.5 llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.6
--- llvm/lib/Transforms/Scalar/Mem2Reg.cpp:1.5	Sat Sep 20 09:38:50 2003
+++ llvm/lib/Transforms/Scalar/Mem2Reg.cpp	Sun Oct  5 16:20:02 2003
@@ -25,6 +25,7 @@
     // getAnalysisUsage - We need dominance frontiers
     //
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.addRequired<DominatorTree>();
       AU.addRequired<DominanceFrontier>();
       AU.addRequired<TargetData>();
       AU.setPreservesCFG();
@@ -41,6 +42,9 @@
   BasicBlock &BB = F.getEntryBlock();  // Get the entry node for the function
 
   bool Changed  = false;
+
+  DominatorTree     &DT = getAnalysis<DominatorTree>();
+  DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
   
   while (1) {
     Allocas.clear();
@@ -54,7 +58,7 @@
 
     if (Allocas.empty()) break;
 
-    PromoteMemToReg(Allocas, getAnalysis<DominanceFrontier>(), TD);
+    PromoteMemToReg(Allocas, DT, DF, TD);
     NumPromoted += Allocas.size();
     Changed = true;
   }


Index: llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp
diff -u llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.14 llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.15
--- llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp:1.14	Sat Sep 20 09:38:50 2003
+++ llvm/lib/Transforms/Scalar/ScalarReplAggregates.cpp	Sun Oct  5 16:20:02 2003
@@ -38,6 +38,7 @@
     // getAnalysisUsage - This pass does not require any passes, but we know it
     // will not alter the CFG, so say so.
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+      AU.addRequired<DominatorTree>();
       AU.addRequired<DominanceFrontier>();
       AU.addRequired<TargetData>();
       AU.setPreservesCFG();
@@ -74,6 +75,8 @@
 bool SROA::performPromotion(Function &F) {
   std::vector<AllocaInst*> Allocas;
   const TargetData &TD = getAnalysis<TargetData>();
+  DominatorTree     &DT = getAnalysis<DominatorTree>();
+  DominanceFrontier &DF = getAnalysis<DominanceFrontier>();
 
   BasicBlock &BB = F.getEntryBlock();  // Get the entry node for the function
 
@@ -91,7 +94,7 @@
 
     if (Allocas.empty()) break;
 
-    PromoteMemToReg(Allocas, getAnalysis<DominanceFrontier>(), TD);
+    PromoteMemToReg(Allocas, DT, DF, TD);
     NumPromoted += Allocas.size();
     Changed = true;
   }