[llvm-commits] CVS: llvm/lib/Target/X86/Makefile

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

Makefile updated: 1.11 -> 1.12

---
Log message:

Be a little more specific about what is begin generated.  Only print
command line if VERBOSE=1


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Diffs of the changes:

Index: llvm/lib/Target/X86/Makefile
diff -u llvm/lib/Target/X86/Makefile:1.11 llvm/lib/Target/X86/Makefile:1.12
--- llvm/lib/Target/X86/Makefile:1.11	Tue Sep  9 15:57:00 2003
+++ llvm/lib/Target/X86/Makefile	Wed Sep 10 14:52:54 2003
@@ -8,28 +8,28 @@
                  X86GenInstrInfo.inc X86GenInstrSelector.inc
 
 X86GenRegisterNames.inc::  X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
-	@echo "Tblgen'ing $<"
-	$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
+	@echo "Building $< register names with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
 
 X86GenRegisterInfo.h.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
-	@echo "Tblgen'ing $<"
-	$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
+	@echo "Building $< register information header with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
 
 X86GenRegisterInfo.inc:: X86.td X86RegisterInfo.td ../Target.td $(TBLGEN)
-	@echo "Tblgen'ing $<"
-	$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
+	@echo "Building $< register information implementation with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
 
 X86GenInstrNames.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
-	@echo "Tblgen'ing $<"
-	$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
+	@echo "Building $< instruction names with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
 
 X86GenInstrInfo.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
-	@echo "Tblgen'ing $<"
-	$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
+	@echo "Building $< instruction information with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
 
 X86GenInstrSelector.inc:: X86.td X86InstrInfo.td ../Target.td $(TBLGEN)
-	@echo "Tblgen'ing $<"
-	$(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
+	@echo "Building $< instruction selector with tblgen"
+	$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
 
 clean::
 	$(VERB) rm -f *.inc