[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/InstrSched:

InstrScheduling.cpp updated: 1.55 -> 1.56

---
Log message:

Remove uses of the NonCopyable class, to make the doxygen output look better


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Diffs of the changes:

Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.55 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.56
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.55	Thu Aug 14 01:09:29 2003
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp	Fri Aug 15 00:20:06 2003
@@ -41,7 +41,10 @@
 // in a single cycle.
 //----------------------------------------------------------------------
 
-class InstrGroup: public NonCopyable {
+class InstrGroup {
+  InstrGroup(const InstrGroup&);       // DO NOT IMPLEMENT
+  void operator=(const InstrGroup&);   // DO NOT IMPLEMENT
+  
 public:
   inline const SchedGraphNode* operator[](unsigned int slotNum) const {
     assert(slotNum  < group.size());
@@ -124,12 +127,14 @@
 // Represents the schedule of machine instructions for a single basic block.
 //----------------------------------------------------------------------
 
-class InstrSchedule: public NonCopyable {
-private:
+class InstrSchedule {
   const unsigned int nslots;
   unsigned int numInstr;
   std::vector<InstrGroup*> groups;		// indexed by cycle number
   std::vector<cycles_t> startTime;		// indexed by node id
+
+  InstrSchedule(InstrSchedule&);   // DO NOT IMPLEMENT
+  void operator=(InstrSchedule&);  // DO NOT IMPLEMENT
   
 public: // iterators
   typedef ScheduleIterator<SchedGraphNode> iterator;
@@ -292,14 +297,15 @@
 // Delay slots are simply indexed by slot number 1 ... numDelaySlots
 //----------------------------------------------------------------------
 
-class DelaySlotInfo: public NonCopyable {
-private:
+class DelaySlotInfo {
   const SchedGraphNode* brNode;
-  unsigned int ndelays;
+  unsigned ndelays;
   std::vector<const SchedGraphNode*> delayNodeVec;
   cycles_t delayedNodeCycle;
-  unsigned int delayedNodeSlotNum;
+  unsigned delayedNodeSlotNum;
   
+  DelaySlotInfo(const DelaySlotInfo &);  // DO NOT IMPLEMENT
+  void operator=(const DelaySlotInfo&);  // DO NOT IMPLEMENT
 public:
   /*ctor*/	DelaySlotInfo		(const SchedGraphNode* _brNode,
 					 unsigned _ndelays)
@@ -334,7 +340,9 @@
 // Represents the schedule of machine instructions for a single basic block.
 //----------------------------------------------------------------------
 
-class SchedulingManager: public NonCopyable {
+class SchedulingManager {
+  SchedulingManager(SchedulingManager &);    // DO NOT IMPLEMENT
+  void operator=(const SchedulingManager &); // DO NOT IMPLEMENT
 public: // publicly accessible data members
   const unsigned nslots;
   const TargetSchedInfo& schedInfo;
@@ -342,7 +350,7 @@
   InstrSchedule isched;
   
 private:
-  unsigned int totalInstrCount;
+  unsigned totalInstrCount;
   cycles_t curTime;
   cycles_t nextEarliestIssueTime;		// next cycle we can issue
   // indexed by slot#