[llvm-commits] CVS: llvm/lib/Reoptimizer/LightWtProfiling/Trigger/RegSaveRestore.h FirstTrigger.cpp
Brian Gaeke
gaeke at cs.uiuc.edu
Tue Aug 5 14:17:01 PDT 2003
Changes in directory llvm/lib/Reoptimizer/LightWtProfiling/Trigger:
RegSaveRestore.h added (r1.1)
FirstTrigger.cpp updated: 1.6 -> 1.7
---
Log message:
Incorporate register save/restore asms into macros in RegSaveRestore.h.
Use these in FirstTrigger.cpp instead of asms.
Add better comments. Fix a lot of extraneous whitespace.
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/LightWtProfiling/Trigger/RegSaveRestore.h
diff -c /dev/null llvm/lib/Reoptimizer/LightWtProfiling/Trigger/RegSaveRestore.h:1.1
*** /dev/null Tue Aug 5 14:16:54 2003
--- llvm/lib/Reoptimizer/LightWtProfiling/Trigger/RegSaveRestore.h Tue Aug 5 14:16:41 2003
***************
*** 0 ****
--- 1,168 ----
+ #ifndef REGSAVERESTORE_H
+ #define REGSAVERESTORE_H
+
+ #define SAVE_I_REGS(i_reg_save) \
+ do { \
+ asm volatile ("stx %%i0, %0": "=m"(i_reg_save[0])); \
+ asm volatile ("stx %%i1, %0": "=m"(i_reg_save[1])); \
+ asm volatile ("stx %%i2, %0": "=m"(i_reg_save[2])); \
+ asm volatile ("stx %%i3, %0": "=m"(i_reg_save[3])); \
+ asm volatile ("stx %%i4, %0": "=m"(i_reg_save[4])); \
+ asm volatile ("stx %%i5, %0": "=m"(i_reg_save[5])); \
+ } while (0)
+
+ #define LOAD_I_REGS(i_reg_save) \
+ do { \
+ asm volatile ("ldx %0, %%i0":: "m"(i_reg_save[0])); \
+ asm volatile ("ldx %0, %%i1":: "m"(i_reg_save[1])); \
+ asm volatile ("ldx %0, %%i2":: "m"(i_reg_save[2])); \
+ asm volatile ("ldx %0, %%i3":: "m"(i_reg_save[3])); \
+ asm volatile ("ldx %0, %%i4":: "m"(i_reg_save[4])); \
+ asm volatile ("ldx %0, %%i5":: "m"(i_reg_save[5])); \
+ } while (0)
+
+ #define SAVE_G1_REG(g1_reg) \
+ asm volatile ("stx %%g1, %0": "=m"(g1_reg))
+
+ #define LOAD_G1_REG(g1_reg) \
+ asm volatile ("ldx %0, %%g1":: "m"(g1_reg))
+
+ #define SAVE_F_REGS_1(f_reg_save) \
+ do { \
+ asm volatile ("st %%f0, %0": "=m"(f_reg_save[0])); \
+ asm volatile ("st %%f1, %0": "=m"(f_reg_save[1])); \
+ asm volatile ("st %%f2, %0": "=m"(f_reg_save[2])); \
+ asm volatile ("st %%f3, %0": "=m"(f_reg_save[3])); \
+ asm volatile ("st %%f4, %0": "=m"(f_reg_save[4])); \
+ asm volatile ("st %%f5, %0": "=m"(f_reg_save[5])); \
+ asm volatile ("st %%f6, %0": "=m"(f_reg_save[6])); \
+ asm volatile ("st %%f7, %0": "=m"(f_reg_save[7])); \
+ asm volatile ("st %%f8, %0": "=m"(f_reg_save[8])); \
+ asm volatile ("st %%f9, %0": "=m"(f_reg_save[9])); \
+ asm volatile ("st %%f10, %0": "=m"(f_reg_save[10])); \
+ asm volatile ("st %%f11, %0": "=m"(f_reg_save[11])); \
+ asm volatile ("st %%f12, %0": "=m"(f_reg_save[12])); \
+ asm volatile ("st %%f13, %0": "=m"(f_reg_save[13])); \
+ asm volatile ("st %%f14, %0": "=m"(f_reg_save[14])); \
+ asm volatile ("st %%f15, %0": "=m"(f_reg_save[15])); \
+ } while (0)
+
+ #define LOAD_F_REGS_1(f_reg_save) \
+ do { \
+ asm volatile ("ld %0, %%f0":: "m"(f_reg_save[0])); \
+ asm volatile ("ld %0, %%f1":: "m"(f_reg_save[1])); \
+ asm volatile ("ld %0, %%f2":: "m"(f_reg_save[2])); \
+ asm volatile ("ld %0, %%f3":: "m"(f_reg_save[3])); \
+ asm volatile ("ld %0, %%f4":: "m"(f_reg_save[4])); \
+ asm volatile ("ld %0, %%f5":: "m"(f_reg_save[5])); \
+ asm volatile ("ld %0, %%f6":: "m"(f_reg_save[6])); \
+ asm volatile ("ld %0, %%f7":: "m"(f_reg_save[7])); \
+ asm volatile ("ld %0, %%f8":: "m"(f_reg_save[8])); \
+ asm volatile ("ld %0, %%f9":: "m"(f_reg_save[9])); \
+ asm volatile ("ld %0, %%f10":: "m"(f_reg_save[10])); \
+ asm volatile ("ld %0, %%f11":: "m"(f_reg_save[11])); \
+ asm volatile ("ld %0, %%f12":: "m"(f_reg_save[12])); \
+ asm volatile ("ld %0, %%f13":: "m"(f_reg_save[13])); \
+ asm volatile ("ld %0, %%f14":: "m"(f_reg_save[14])); \
+ asm volatile ("ld %0, %%f15":: "m"(f_reg_save[15])); \
+ } while (0)
+
+ #define SAVE_F_REGS_2(f_reg_save) \
+ do { \
+ asm volatile ("st %%f16, %0": "=m"(f_reg_save[16])); \
+ asm volatile ("st %%f17, %0": "=m"(f_reg_save[17])); \
+ asm volatile ("st %%f18, %0": "=m"(f_reg_save[18])); \
+ asm volatile ("st %%f19, %0": "=m"(f_reg_save[19])); \
+ asm volatile ("st %%f20, %0": "=m"(f_reg_save[20])); \
+ asm volatile ("st %%f21, %0": "=m"(f_reg_save[21])); \
+ asm volatile ("st %%f22, %0": "=m"(f_reg_save[22])); \
+ asm volatile ("st %%f23, %0": "=m"(f_reg_save[23])); \
+ asm volatile ("st %%f24, %0": "=m"(f_reg_save[24])); \
+ asm volatile ("st %%f25, %0": "=m"(f_reg_save[25])); \
+ asm volatile ("st %%f26, %0": "=m"(f_reg_save[26])); \
+ asm volatile ("st %%f27, %0": "=m"(f_reg_save[27])); \
+ asm volatile ("st %%f28, %0": "=m"(f_reg_save[28])); \
+ asm volatile ("st %%f29, %0": "=m"(f_reg_save[29])); \
+ asm volatile ("st %%f30, %0": "=m"(f_reg_save[30])); \
+ asm volatile ("st %%f31, %0": "=m"(f_reg_save[31])); \
+ } while (0)
+
+ #define LOAD_F_REGS_2(f_reg_save) \
+ do { \
+ asm volatile ("ld %0, %%f16":: "m"(f_reg_save[16])); \
+ asm volatile ("ld %0, %%f17":: "m"(f_reg_save[17])); \
+ asm volatile ("ld %0, %%f18":: "m"(f_reg_save[18])); \
+ asm volatile ("ld %0, %%f19":: "m"(f_reg_save[19])); \
+ asm volatile ("ld %0, %%f20":: "m"(f_reg_save[20])); \
+ asm volatile ("ld %0, %%f21":: "m"(f_reg_save[21])); \
+ asm volatile ("ld %0, %%f22":: "m"(f_reg_save[22])); \
+ asm volatile ("ld %0, %%f23":: "m"(f_reg_save[23])); \
+ asm volatile ("ld %0, %%f24":: "m"(f_reg_save[24])); \
+ asm volatile ("ld %0, %%f25":: "m"(f_reg_save[25])); \
+ asm volatile ("ld %0, %%f26":: "m"(f_reg_save[26])); \
+ asm volatile ("ld %0, %%f27":: "m"(f_reg_save[27])); \
+ asm volatile ("ld %0, %%f28":: "m"(f_reg_save[28])); \
+ asm volatile ("ld %0, %%f29":: "m"(f_reg_save[29])); \
+ asm volatile ("ld %0, %%f30":: "m"(f_reg_save[30])); \
+ asm volatile ("ld %0, %%f31":: "m"(f_reg_save[31])); \
+ } while (0)
+
+ #define SAVE_FD_REGS(fd_reg_save) \
+ do { \
+ asm volatile ("std %%f32, %0": "=m"(fd_reg_save[32/2-16])); \
+ asm volatile ("std %%f34, %0": "=m"(fd_reg_save[34/2-16])); \
+ asm volatile ("std %%f36, %0": "=m"(fd_reg_save[36/2-16])); \
+ asm volatile ("std %%f38, %0": "=m"(fd_reg_save[38/2-16])); \
+ asm volatile ("std %%f40, %0": "=m"(fd_reg_save[40/2-16])); \
+ asm volatile ("std %%f42, %0": "=m"(fd_reg_save[42/2-16])); \
+ asm volatile ("std %%f44, %0": "=m"(fd_reg_save[44/2-16])); \
+ asm volatile ("std %%f46, %0": "=m"(fd_reg_save[46/2-16])); \
+ asm volatile ("std %%f48, %0": "=m"(fd_reg_save[48/2-16])); \
+ asm volatile ("std %%f50, %0": "=m"(fd_reg_save[50/2-16])); \
+ asm volatile ("std %%f52, %0": "=m"(fd_reg_save[52/2-16])); \
+ asm volatile ("std %%f54, %0": "=m"(fd_reg_save[54/2-16])); \
+ asm volatile ("std %%f56, %0": "=m"(fd_reg_save[56/2-16])); \
+ asm volatile ("std %%f58, %0": "=m"(fd_reg_save[58/2-16])); \
+ asm volatile ("std %%f60, %0": "=m"(fd_reg_save[60/2-16])); \
+ asm volatile ("std %%f62, %0": "=m"(fd_reg_save[62/2-16])); \
+ } while (0)
+
+ #define LOAD_FD_REGS(fd_reg_save) \
+ do { \
+ asm volatile ("ldd %0, %%f32":: "m"(fd_reg_save[32/2-16])); \
+ asm volatile ("ldd %0, %%f34":: "m"(fd_reg_save[34/2-16])); \
+ asm volatile ("ldd %0, %%f36":: "m"(fd_reg_save[36/2-16])); \
+ asm volatile ("ldd %0, %%f38":: "m"(fd_reg_save[38/2-16])); \
+ asm volatile ("ldd %0, %%f40":: "m"(fd_reg_save[40/2-16])); \
+ asm volatile ("ldd %0, %%f42":: "m"(fd_reg_save[42/2-16])); \
+ asm volatile ("ldd %0, %%f44":: "m"(fd_reg_save[44/2-16])); \
+ asm volatile ("ldd %0, %%f46":: "m"(fd_reg_save[46/2-16])); \
+ asm volatile ("ldd %0, %%f48":: "m"(fd_reg_save[48/2-16])); \
+ asm volatile ("ldd %0, %%f50":: "m"(fd_reg_save[50/2-16])); \
+ asm volatile ("ldd %0, %%f52":: "m"(fd_reg_save[52/2-16])); \
+ asm volatile ("ldd %0, %%f54":: "m"(fd_reg_save[54/2-16])); \
+ asm volatile ("ldd %0, %%f56":: "m"(fd_reg_save[56/2-16])); \
+ asm volatile ("ldd %0, %%f58":: "m"(fd_reg_save[58/2-16])); \
+ asm volatile ("ldd %0, %%f60":: "m"(fd_reg_save[60/2-16])); \
+ asm volatile ("ldd %0, %%f62":: "m"(fd_reg_save[62/2-16])); \
+ } while (0)
+
+ #define SAVE_FSR_REG(fsr_reg) \
+ asm volatile ("stx %%fsr, %0": "=m" (fsr_reg))
+
+ #define LOAD_FSR_REG(fsr_reg) \
+ asm volatile ("ldx %0, %%fsr":: "m"(fsr_reg))
+
+ #define SAVE_FPRS_REG(fprs_reg) \
+ asm volatile ("rd %%fprs, %0": "=r"(fprs_reg))
+
+ #define LOAD_FPRS_REG(fprs_reg) \
+ asm volatile ("wr %0, 0, %%fprs":: "r"(fprs_reg))
+
+ #define SAVE_CCR_REG(ccr_reg) \
+ asm volatile ("rd %%ccr, %0": "=r"(ccr_reg))
+
+ #define LOAD_CCR_REG(ccr_reg) \
+ asm volatile ("wr %0, 0, %%ccr":: "r"(ccr_reg))
+
+ #endif // REGSAVERESTORE_H
Index: llvm/lib/Reoptimizer/LightWtProfiling/Trigger/FirstTrigger.cpp
diff -u llvm/lib/Reoptimizer/LightWtProfiling/Trigger/FirstTrigger.cpp:1.6 llvm/lib/Reoptimizer/LightWtProfiling/Trigger/FirstTrigger.cpp:1.7
--- llvm/lib/Reoptimizer/LightWtProfiling/Trigger/FirstTrigger.cpp:1.6 Tue Aug 5 13:21:26 2003
+++ llvm/lib/Reoptimizer/LightWtProfiling/Trigger/FirstTrigger.cpp Tue Aug 5 14:16:41 2003
@@ -20,6 +20,7 @@
#ifdef __sparc
#include <libcpc.h>
#endif
+#include "RegSaveRestore.h"
using namespace std;
@@ -80,8 +81,6 @@
}
extern "C" void llvm_first_trigger(){
-
- //save regs
uint64_t i_reg_save[6];
uint32_t f_reg_save[32];
uint64_t fd_reg_save[16];
@@ -90,119 +89,58 @@
uint64_t fsr_reg;
uint64_t g1_reg;
- //#ifdef __sparc
- asm volatile ("stx %%i0, %0": "=m"(i_reg_save[0]));
- asm volatile ("stx %%i1, %0": "=m"(i_reg_save[1]));
- asm volatile ("stx %%i2, %0": "=m"(i_reg_save[2]));
- asm volatile ("stx %%i3, %0": "=m"(i_reg_save[3]));
- asm volatile ("stx %%i4, %0": "=m"(i_reg_save[4]));
- asm volatile ("stx %%i5, %0": "=m"(i_reg_save[5]));
-
- asm volatile ("stx %%g1, %0": "=m"(g1_reg));
- asm volatile ("st %%f0, %0": "=m"(f_reg_save[0]));
- asm volatile ("st %%f1, %0": "=m"(f_reg_save[1]));
- asm volatile ("st %%f2, %0": "=m"(f_reg_save[2]));
- asm volatile ("st %%f3, %0": "=m"(f_reg_save[3]));
- asm volatile ("st %%f4, %0": "=m"(f_reg_save[4]));
- asm volatile ("st %%f5, %0": "=m"(f_reg_save[5]));
- asm volatile ("st %%f6, %0": "=m"(f_reg_save[6]));
- asm volatile ("st %%f7, %0": "=m"(f_reg_save[7]));
- asm volatile ("st %%f8, %0": "=m"(f_reg_save[8]));
- asm volatile ("st %%f9, %0": "=m"(f_reg_save[9]));
- asm volatile ("st %%f10, %0": "=m"(f_reg_save[10]));
- asm volatile ("st %%f11, %0": "=m"(f_reg_save[11]));
- asm volatile ("st %%f12, %0": "=m"(f_reg_save[12]));
- asm volatile ("st %%f13, %0": "=m"(f_reg_save[13]));
- asm volatile ("st %%f14, %0": "=m"(f_reg_save[14]));
- asm volatile ("st %%f15, %0": "=m"(f_reg_save[15]));
-
- /*
- asm volatile ("st %%f16, %0": "=m"(f_reg_save[16]));
- asm volatile ("st %%f17, %0": "=m"(f_reg_save[17]));
- asm volatile ("st %%f18, %0": "=m"(f_reg_save[18]));
- asm volatile ("st %%f19, %0": "=m"(f_reg_save[19]));
- asm volatile ("st %%f20, %0": "=m"(f_reg_save[20]));
- asm volatile ("st %%f21, %0": "=m"(f_reg_save[21]));
- asm volatile ("st %%f22, %0": "=m"(f_reg_save[22]));
- asm volatile ("st %%f23, %0": "=m"(f_reg_save[23]));
- asm volatile ("st %%f24, %0": "=m"(f_reg_save[24]));
- asm volatile ("st %%f25, %0": "=m"(f_reg_save[25]));
- asm volatile ("st %%f26, %0": "=m"(f_reg_save[26]));
- asm volatile ("st %%f27, %0": "=m"(f_reg_save[27]));
- asm volatile ("st %%f28, %0": "=m"(f_reg_save[28]));
- asm volatile ("st %%f29, %0": "=m"(f_reg_save[29]));
- asm volatile ("st %%f30, %0": "=m"(f_reg_save[30]));
- asm volatile ("st %%f31, %0": "=m"(f_reg_save[31]));*/
-
- asm volatile ("std %%f32, %0": "=m"(fd_reg_save[32/2-16]));
- asm volatile ("std %%f34, %0": "=m"(fd_reg_save[34/2-16]));
- asm volatile ("std %%f36, %0": "=m"(fd_reg_save[36/2-16]));
- asm volatile ("std %%f38, %0": "=m"(fd_reg_save[38/2-16]));
- asm volatile ("std %%f40, %0": "=m"(fd_reg_save[40/2-16]));
- asm volatile ("std %%f42, %0": "=m"(fd_reg_save[42/2-16]));
- asm volatile ("std %%f44, %0": "=m"(fd_reg_save[44/2-16]));
- asm volatile ("std %%f46, %0": "=m"(fd_reg_save[46/2-16]));
- //*/
- asm volatile ("std %%f48, %0": "=m"(fd_reg_save[48/2-16]));
- asm volatile ("std %%f50, %0": "=m"(fd_reg_save[50/2-16]));
- asm volatile ("std %%f52, %0": "=m"(fd_reg_save[52/2-16]));
- asm volatile ("std %%f54, %0": "=m"(fd_reg_save[54/2-16]));
- asm volatile ("std %%f56, %0": "=m"(fd_reg_save[56/2-16]));
- asm volatile ("std %%f58, %0": "=m"(fd_reg_save[58/2-16]));
- asm volatile ("std %%f60, %0": "=m"(fd_reg_save[60/2-16]));
- asm volatile ("std %%f62, %0": "=m"(fd_reg_save[62/2-16]));
-
- asm volatile ("stx %%fsr, %0": "=m" (fsr_reg));
- asm volatile ("rd %%fprs, %0": "=r"(fprs_reg));
-
- asm volatile ("rd %%ccr, %0": "=r"(ccr_reg));
-
- //#endif
- //a map of counters
+ // Save registers on the stack, in the local variables declared above.
+ // FIXME: Why don't we save the upper f registers?
+ SAVE_I_REGS(i_reg_save);
+ SAVE_G1_REG(g1_reg);
+ SAVE_F_REGS_1(f_reg_save);
+ // SAVE_F_REGS_2(f_reg_save);
+ SAVE_FD_REGS(fd_reg_save);
+ SAVE_FSR_REG(fsr_reg);
+ SAVE_FPRS_REG(fprs_reg);
+ SAVE_CCR_REG(ccr_reg);
+ // Maps of counters we use:
static map<uint64_t, int> counterMap;
static map<uint64_t, int> seenOccur;
+ // FIXME: What is brAddr?
uint64_t brAddr;
-
#ifdef __sparc
asm("add %%i7, %1, %0":"=r"(brAddr):"i" (0));
#else
assert(false && "Case not handled for this processor architecture!");
#endif
- //if(counterMap[brAddr] > 200)
- //return;
+ // Increment the counter for this branch, and check it against
+ // THRESHOLD_LEVEL_1. If it exceeds the threshold, we may have to
+ // generate second-level instrumentation (SLI).
if(++counterMap[brAddr] > reopt_threshold){
-
counterMap.erase(brAddr);
-
//std::cerr<<"Originally Removed from addr: "<<(void *)brAddr<<"\n";
+ // Scan forward through memory starting from brAddr, looking for a branch
+ // instruction.
char offst = 8;
unsigned int brInst = vm->readInstrFrmVm(brAddr + offst, tr, tr2);
-
while(!isBranchInstr(brInst)){
offst += 4;
brInst = vm->readInstrFrmVm(brAddr + offst, tr, tr2);
}
-
assert(isBranchInstr(brInst) && "Not a branch!");
-
uint64_t brTarget = getBranchTarget(brInst, brAddr+offst);
-
firstTriggerAddr[brTarget] = brAddr;
- //check if tracecache already has optimized code. If yes,
- //do not generate SLI
- if(!tr->hasTraceAddr(brTarget, brAddr+offst)){
+ // Check if trace cache already has optimized code. If it does,
+ // we do not generate SLI.
+ if(!tr->hasTraceAddr(brTarget, brAddr+offst)) {
+ // No optimized code in trace cache; generate SLI now.
getFirstTrace(brTarget, brAddr+offst, 100, vm, tr);
- }
- else{
+ } else {
#ifdef GET_ALL_INFO
std::cerr<<"SLI-exists\t"<<(void *)brTarget<<"\t"<<(void *)(brTarget+offst)<<"\n";
#endif
- //write a branch going to top of trace in tr
+ // Write a branch going to the top of the trace in tr.
uint64_t traceAddrInTC = tr->getStartAddr(brTarget);
vm->writeInstToVM(traceAddrInTC, tr->getAddr(brTarget));
@@ -216,70 +154,16 @@
doFlush(brAddr-8, brAddr+16);
}
- //#ifdef __sparc
fprs_reg ^= 0;
ccr_reg ^= 0;
- asm volatile ("wr %0, 0, %%ccr":: "r"(ccr_reg));
- asm volatile ("ldx %0, %%i0":: "m"(i_reg_save[0]));
- asm volatile ("ldx %0, %%i1":: "m"(i_reg_save[1]));
- asm volatile ("ldx %0, %%i2":: "m"(i_reg_save[2]));
- asm volatile ("ldx %0, %%i3":: "m"(i_reg_save[3]));
- asm volatile ("ldx %0, %%i4":: "m"(i_reg_save[4]));
- asm volatile ("ldx %0, %%i5":: "m"(i_reg_save[5]));
-
- asm volatile ("wr %0, 0, %%fprs":: "r"(fprs_reg));
- asm volatile ("ldx %0, %%g1":: "m"(g1_reg));
- asm volatile ("ld %0, %%f0":: "m"(f_reg_save[0]));
- asm volatile ("ld %0, %%f1":: "m"(f_reg_save[1]));
- asm volatile ("ld %0, %%f2":: "m"(f_reg_save[2]));
- asm volatile ("ld %0, %%f3":: "m"(f_reg_save[3]));
- asm volatile ("ld %0, %%f4":: "m"(f_reg_save[4]));
- asm volatile ("ld %0, %%f5":: "m"(f_reg_save[5]));
- asm volatile ("ld %0, %%f6":: "m"(f_reg_save[6]));
- asm volatile ("ld %0, %%f7":: "m"(f_reg_save[7]));
- asm volatile ("ld %0, %%f8":: "m"(f_reg_save[8]));
- asm volatile ("ld %0, %%f9":: "m"(f_reg_save[9]));
- asm volatile ("ld %0, %%f10":: "m"(f_reg_save[10]));
- asm volatile ("ld %0, %%f11":: "m"(f_reg_save[11]));
- asm volatile ("ld %0, %%f12":: "m"(f_reg_save[12]));
- asm volatile ("ld %0, %%f13":: "m"(f_reg_save[13]));
- asm volatile ("ld %0, %%f14":: "m"(f_reg_save[14]));
- asm volatile ("ld %0, %%f15":: "m"(f_reg_save[15]));
- /*
- asm volatile ("ld %0, %%f16":: "m"(f_reg_save[16]));
- asm volatile ("ld %0, %%f17":: "m"(f_reg_save[17]));
- asm volatile ("ld %0, %%f18":: "m"(f_reg_save[18]));
- asm volatile ("ld %0, %%f19":: "m"(f_reg_save[19]));
- asm volatile ("ld %0, %%f20":: "m"(f_reg_save[20]));
- asm volatile ("ld %0, %%f21":: "m"(f_reg_save[21]));
- asm volatile ("ld %0, %%f22":: "m"(f_reg_save[22]));
- asm volatile ("ld %0, %%f23":: "m"(f_reg_save[23]));
- asm volatile ("ld %0, %%f24":: "m"(f_reg_save[24]));
- asm volatile ("ld %0, %%f25":: "m"(f_reg_save[25]));
- asm volatile ("ld %0, %%f26":: "m"(f_reg_save[26]));
- asm volatile ("ld %0, %%f27":: "m"(f_reg_save[27]));
- asm volatile ("ld %0, %%f28":: "m"(f_reg_save[28]));
- asm volatile ("ld %0, %%f29":: "m"(f_reg_save[29]));
- asm volatile ("ld %0, %%f30":: "m"(f_reg_save[30]));
- asm volatile ("ld %0, %%f31":: "m"(f_reg_save[31]));*/
- asm volatile ("ldd %0, %%f32":: "m"(fd_reg_save[32/2-16]));
- asm volatile ("ldd %0, %%f34":: "m"(fd_reg_save[34/2-16]));
- asm volatile ("ldd %0, %%f36":: "m"(fd_reg_save[36/2-16]));
- asm volatile ("ldd %0, %%f38":: "m"(fd_reg_save[38/2-16]));
- asm volatile ("ldd %0, %%f40":: "m"(fd_reg_save[40/2-16]));
- asm volatile ("ldd %0, %%f42":: "m"(fd_reg_save[42/2-16]));
- asm volatile ("ldd %0, %%f44":: "m"(fd_reg_save[44/2-16]));
- asm volatile ("ldd %0, %%f46":: "m"(fd_reg_save[46/2-16]));
- //*/
- asm volatile ("ldd %0, %%f48":: "m"(fd_reg_save[48/2-16]));
- asm volatile ("ldd %0, %%f50":: "m"(fd_reg_save[50/2-16]));
- asm volatile ("ldd %0, %%f52":: "m"(fd_reg_save[52/2-16]));
- asm volatile ("ldd %0, %%f54":: "m"(fd_reg_save[54/2-16]));
- asm volatile ("ldd %0, %%f56":: "m"(fd_reg_save[56/2-16]));
- asm volatile ("ldd %0, %%f58":: "m"(fd_reg_save[58/2-16]));
- asm volatile ("ldd %0, %%f60":: "m"(fd_reg_save[60/2-16]));
- asm volatile ("ldd %0, %%f62":: "m"(fd_reg_save[62/2-16]));
- asm volatile ("ldx %0, %%fsr":: "m"(fsr_reg));
- //#endif
+ // Restore registers from local variables, and return to executing code.
+ LOAD_CCR_REG(ccr_reg);
+ LOAD_I_REGS(i_reg_save);
+ LOAD_FPRS_REG(fprs_reg);
+ LOAD_G1_REG(g1_reg);
+ LOAD_F_REGS_1(f_reg_save);
+ // LOAD_F_REGS_2(f_reg_save);
+ LOAD_FD_REGS(fd_reg_save);
+ LOAD_FSR_REG(fsr_reg);
}
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