[llvm-commits] CVS: llvm/lib/Target/Target.td

[Chris Lattner]

Changes in directory llvm/lib/Target:

Target.td updated: 1.4 -> 1.5

---
Log message:

Add all of the necessary classes to describe the contents of the MRegister.h implementation
for a target. 


---
Diffs of the changes:

Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.4 llvm/lib/Target/Target.td:1.5
--- llvm/lib/Target/Target.td:1.4	Tue Jul 29 18:07:13 2003
+++ llvm/lib/Target/Target.td	Wed Jul 30 00:50:12 2003
@@ -5,9 +5,14 @@
 //
 //===----------------------------------------------------------------------===//
 
+
+//===----------------------------------------------------------------------===//
+//
 // Value types - These values correspond to the register types defined in the
 // ValueTypes.h file.
+
 class ValueType { string Namespace = "MVT"; }
+
 def i1   : ValueType;    // One bit boolean value
 def i8   : ValueType;    // 8-bit integer value
 def i16  : ValueType;    // 16-bit integer value
@@ -19,10 +24,44 @@
 def f80  : ValueType;    // 80-bit floating point value
 def f128 : ValueType;    // 128-bit floating point value
 
+
+//===----------------------------------------------------------------------===//
+// Register file description - These classes are used to fill in the target
+// description classes in llvm/Target/MRegisterInfo.h
+
+
+// Register - You should define one instance of this class for each register in
+// the target machine.
+//
 class Register {
   string Namespace = "";
-  ValueType RegType;
 }
+
+// RegisterAliases - You should define instances of this class to indicate which
+// registers in the register file are aliased together.  This allows the code
+// generator to be careful not to put two values with overlapping live ranges
+// into registers which alias.
+//
+class RegisterAliases<Register reg, list<Register> aliases> {
+  Register Reg = reg;
+  list<Register> Aliases = aliases;
+}
+
+// RegisterClass - Now that all of the registers are defined, and aliases
+// between registers are defined, specify which registers belong to which
+// register classes.  This also defines the default allocation order of
+// registers by register allocators.
+//
+class RegisterClass<ValueType regType, int alignment, list<Register> regList> {
+  ValueType RegType = regType;
+  int Alignment = alignment;
+  list<Register> MemberList = regList;
+}
+
+
+//===----------------------------------------------------------------------===//
+// Instruction set description - 
+//
 
 class Instruction {
   string Name;          // The opcode string for this instruction