[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.117 -> 1.118

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Log message:

Use target specific interface instead of forcing it to be target-generic


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Diffs of the changes:

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.117 llvm/lib/Target/X86/InstSelectSimple.cpp:1.118
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.117	Sat Jul 26 18:49:58 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Wed Jul 30 00:33:48 2003
@@ -219,9 +219,12 @@
     /// of the long value.
     ///
     unsigned makeAnotherReg(const Type *Ty) {
+      assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
+             "Current target doesn't have X86 reg info??");
+      const X86RegisterInfo *MRI =
+        static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
       if (Ty == Type::LongTy || Ty == Type::ULongTy) {
-	const TargetRegisterClass *RC =
-	  TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
+	const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
 	// Create the lower part
 	F->getSSARegMap()->createVirtualRegister(RC);
 	// Create the upper part.
@@ -229,8 +232,7 @@
       }
 
       // Add the mapping of regnumber => reg class to MachineFunction
-      const TargetRegisterClass *RC =
-	TM.getRegisterInfo()->getRegClassForType(Ty);
+      const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
       return F->getSSARegMap()->createVirtualRegister(RC);
     }