[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td

[Misha Brukman]

Changes in directory llvm/lib/Target/Sparc:

SparcV9_F3.td updated: 1.12 -> 1.13

---
Log message:

Removed unnecessary assignment (it was taken care by a superclass) and clarified
some comments.


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Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.12 llvm/lib/Target/Sparc/SparcV9_F3.td:1.13
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.12	Wed Jul  2 14:37:48 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Mon Jul  7 17:18:06 2003
@@ -30,7 +30,6 @@
 class F3_rs1rs2rd : F3_rs1rs2 {
   bits<5> rd;
   set Inst{29-25} = rd;
-  set Inst{4-0} = rs2;
 }
 
 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
@@ -56,7 +55,7 @@
   set Inst{4-0} = rs2;
 }
 
-// F3_rs2rd - Common class of instructions use rs2 and rd, but not rs1
+// F3_rs2rd - Common class of instructions that use rs2 and rd, but not rs1
 class F3_rs2rd : F3_rs2 {
   bits<5> rd;
   set Inst{29-25} = rd;
@@ -127,8 +126,8 @@
   set op3  = op3val;
   set Name = name;
   set Inst{29-25} = 0; // don't care
-  set Inst{13}  = 0;
-  set Inst{12-5} = 0; // don't care
+  set Inst{13} = 0;    // i field = 0
+  set Inst{12-5} = 0;  // don't care
 }
 
 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
@@ -137,7 +136,7 @@
   set op3  = op3Val;
   set Name = name;
   set Inst{29-25} = 0; // don't care
-  set Inst{13}  = 1;
+  set Inst{13} = 1;    // i field = 1
   set Inst{12-0} = simm;
 }
 
@@ -148,7 +147,7 @@
   set Name = name;
   set Inst{13} = 0;           // i field = 0
   set Inst{12-10} = rcondVal; // rcond field
-  set Inst{9-5} = 0; // don't care
+  set Inst{9-5} = 0;          // don't care
 }
 
 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,