[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcV9_F3.td SparcV9_F4.td
Misha Brukman
brukman at cs.uiuc.edu
Wed Jul 2 14:38:01 PDT 2003
Changes in directory llvm/lib/Target/Sparc:
SparcV9_F3.td updated: 1.11 -> 1.12
SparcV9_F4.td updated: 1.5 -> 1.6
---
Log message:
* Force all "don't care" bits to 0 so that there are absolutely no unset bits in
the TableGen descriptions; all unset bits are thus errors.
* As a result, found and fixed instructions where some operands were not
actually assigned into the right portion of the instruction.
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.11 llvm/lib/Target/Sparc/SparcV9_F3.td:1.12
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.11 Thu Jun 5 18:35:11 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td Wed Jul 2 14:37:48 2003
@@ -95,7 +95,7 @@
set op3 = op3val;
set Name = name;
set Inst{13} = 0; // i field = 0
- //set Inst{12-5} = dontcare;
+ set Inst{12-5} = 0; // don't care
}
// The store instructions seem to like to see rd first, then rs1 and rs2
@@ -104,7 +104,7 @@
set op3 = op3val;
set Name = name;
set Inst{13} = 0; // i field = 0
- //set Inst{12-5} = dontcare;
+ set Inst{12-5} = 0; // don't care
}
class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
@@ -126,7 +126,9 @@
set op = opVal;
set op3 = op3val;
set Name = name;
+ set Inst{29-25} = 0; // don't care
set Inst{13} = 0;
+ set Inst{12-5} = 0; // don't care
}
class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
@@ -134,7 +136,7 @@
set op = opVal;
set op3 = op3Val;
set Name = name;
- //set Inst{29-25} = dontcare;
+ set Inst{29-25} = 0; // don't care
set Inst{13} = 1;
set Inst{12-0} = simm;
}
@@ -146,6 +148,7 @@
set Name = name;
set Inst{13} = 0; // i field = 0
set Inst{12-10} = rcondVal; // rcond field
+ set Inst{9-5} = 0; // don't care
}
class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
@@ -156,8 +159,10 @@
set op = opVal;
set op3 = op3Val;
set Name = name;
+ set Inst{29-25} = rd;
set Inst{13} = 1; // i field = 1
set Inst{12-10} = rcondVal; // rcond field
+ set Inst{9-0} = simm10;
}
//FIXME: classes 7-10 not defined!!
@@ -169,7 +174,7 @@
set Name = name;
set Inst{13} = 0; // i field = 0
set Inst{12} = x;
- //set Inst{11-5} = dontcare;
+ set Inst{11-5} = 0; // don't care
}
class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
@@ -182,7 +187,7 @@
set Inst{29-25} = rd;
set Inst{13} = 1; // i field = 1
set Inst{12} = 0; // x field = 0
- //set Inst{11-5} = dontcare;
+ set Inst{11-5} = 0; // don't care
set Inst{4-0} = shcnt;
}
@@ -196,7 +201,7 @@
set Inst{29-25} = rd;
set Inst{13} = 1; // i field = 1
set Inst{12} = 1; // x field = 1
- //set Inst{11-6} = dontcare;
+ set Inst{11-6} = 0; // don't care
set Inst{5-0} = shcnt;
}
@@ -205,7 +210,7 @@
set op = opVal;
set op3 = op3Val;
set Name = name;
- //set Inst{18-14} = dontcare;
+ set Inst{18-14} = 0; // don't care
set Inst{13-5} = opfVal;
}
@@ -218,6 +223,7 @@
set op = opVal;
set op3 = op3Val;
set Name = name;
+ set Inst{29-27} = 0; // defined to be zero
set Inst{26-25} = cc;
set Inst{18-14} = rs1;
set Inst{13-5} = opfVal;
@@ -236,7 +242,7 @@
set op = opVal;
set op3 = op3Val;
set Name = name;
- //Inst{13-0} = dontcare;
+ set Inst{13-0} = 0; // don't care
}
class F3_18<bits<5> fcn, string name> : F3 {
@@ -244,14 +250,14 @@
set op3 = 0b111110;
set Name = name;
set Inst{29-25} = fcn;
- //set Inst{18-0 } = dontcare;
+ set Inst{18-0 } = 0; // don't care;
}
class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
set op = opVal;
set op3 = op3Val;
set Name = name;
- //Inst{18-0} = dontcare;
+ set Inst{18-0} = 0; // don't care
}
// FIXME: class F3_20
Index: llvm/lib/Target/Sparc/SparcV9_F4.td
diff -u llvm/lib/Target/Sparc/SparcV9_F4.td:1.5 llvm/lib/Target/Sparc/SparcV9_F4.td:1.6
--- llvm/lib/Target/Sparc/SparcV9_F4.td:1.5 Wed Jul 2 13:27:47 2003
+++ llvm/lib/Target/Sparc/SparcV9_F4.td Wed Jul 2 14:37:48 2003
@@ -14,14 +14,12 @@
// F4_rs1 - Common class of instructions that use an rs1 field
class F4_rs1 : F4 {
bits<5> rs1;
- //set Inst{29-25} = dontcare;
set Inst{18-14} = rs1;
}
// F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
class F4_rs1rs2 : F4_rs1 {
bits<5> rs2;
- //set Inst{12-5} = dontcare;
set Inst{4-0} = rs2;
}
@@ -64,7 +62,7 @@
set Name = name;
set Inst{13} = 0; // i bit
set Inst{12-11} = cc;
- //set Inst{10-5} = dontcare;
+ set Inst{10-5} = 0; // don't care
}
class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
@@ -88,7 +86,7 @@
set Name = name;
set Inst{29-25} = rd;
set Inst{13} = 0; // i bit
- //set Inst{10-5} = dontcare;
+ set Inst{10-5} = 0; // don't care
set Inst{4-0} = rs2;
}
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