[llvm-commits] CVS: llvm/tools/lli/JIT/SparcEmitter.cpp

[Brian Gaeke]

Changes in directory llvm/tools/lli/JIT:

SparcEmitter.cpp updated: 1.5 -> 1.6

---
Log message:

Fix induction variable name clash in for loops, in finishFunction().
Modify new MachineOperand so that its flags match the old MachineOperand's
 flags, for the flags that matter.


---
Diffs of the changes:

Index: llvm/tools/lli/JIT/SparcEmitter.cpp
diff -u llvm/tools/lli/JIT/SparcEmitter.cpp:1.5 llvm/tools/lli/JIT/SparcEmitter.cpp:1.6
--- llvm/tools/lli/JIT/SparcEmitter.cpp:1.5	Sat May 31 01:26:48 2003
+++ llvm/tools/lli/JIT/SparcEmitter.cpp	Sun Jun  1 17:08:29 2003
@@ -98,16 +98,21 @@
     unsigned *Ref = BBRefs[i].second.first;
     MachineInstr *MI = BBRefs[i].second.second;
     std::cerr << "attempting to resolve BB: " << i << "\n";
-    for (unsigned i=0, e = MI->getNumOperands(); i != e; ++i) {
-      MachineOperand &op = MI->getOperand(i);
+    for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
+      MachineOperand &op = MI->getOperand(ii);
       if (op.isPCRelativeDisp()) {
         // the instruction's branch target is made such that it branches to
         // PC + (br target * 4), so undo that arithmetic here:
         // Location is the target of the branch
         // Ref is the location of the instruction, and hence the PC
         unsigned branchTarget = (Location - (long)Ref) >> 2;
-        MI->SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed,
+        MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
                                    branchTarget);
+        // Copy the flags.
+        if (op.opLoBits32()) { MI->setOperandLo32(ii); }
+        else if (op.opHiBits32()) { MI->setOperandHi32(ii); }
+        else if (op.opLoBits64()) { MI->setOperandLo64(ii); }
+        else if (op.opHiBits64()) { MI->setOperandHi64(ii); }
         std::cerr << "Rewrote BB ref: ";
         unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
         *Ref = fixedInstr;