[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sat May 31 22:39:01 PDT 2003
Changes in directory llvm/lib/Target/X86:
InstSelectSimple.cpp updated: 1.102 -> 1.103
---
Log message:
* Implement cast (long|ulong) to bool
* Fix cast of (short|ushort|int|uint) to bool to work right
---
Diffs of the changes:
Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.102 llvm/lib/Target/X86/InstSelectSimple.cpp:1.103
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.102 Sat May 31 20:56:54 2003
+++ llvm/lib/Target/X86/InstSelectSimple.cpp Sat May 31 22:38:24 2003
@@ -1552,10 +1552,28 @@
// Implement casts to bool by using compare on the operand followed by set if
// not zero on the result.
if (DestTy == Type::BoolTy) {
- if (SrcClass == cFP || SrcClass == cLong)
- abort(); // FIXME: implement cast (long & FP) to bool
-
- BMI(BB, IP, X86::CMPri8, 2).addReg(SrcReg).addZImm(0);
+ switch (SrcClass) {
+ case cByte:
+ BMI(BB, IP, X86::TESTrr8, 2).addReg(SrcReg).addReg(SrcReg);
+ break;
+ case cShort:
+ BMI(BB, IP, X86::TESTrr16, 2).addReg(SrcReg).addReg(SrcReg);
+ break;
+ case cInt:
+ BMI(BB, IP, X86::TESTrr32, 2).addReg(SrcReg).addReg(SrcReg);
+ break;
+ case cLong: {
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ BMI(BB, IP, X86::ORrr32, 2, TmpReg).addReg(SrcReg).addReg(SrcReg+1);
+ break;
+ }
+ case cFP:
+ assert(0 && "FIXME: implement cast FP to bool");
+ abort();
+ }
+
+ // If the zero flag is not set, then the value is true, set the byte to
+ // true.
BMI(BB, IP, X86::SETNEr, 1, DestReg);
return;
}
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