[llvm-commits] CVS: llvm/lib/Reoptimizer/Trigger/Trigger.cpp
Anand Shukla
ashukla at cs.uiuc.edu
Sat May 31 21:36:37 PDT 2003
Changes in directory llvm/lib/Reoptimizer/Trigger:
Trigger.cpp updated: 1.16 -> 1.17
---
Log message:
Trigger function modified to use the new bininterface for binary modification
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/Trigger/Trigger.cpp
diff -u llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.16 llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.17
--- llvm/lib/Reoptimizer/Trigger/Trigger.cpp:1.16 Wed Feb 19 13:26:38 2003
+++ llvm/lib/Reoptimizer/Trigger/Trigger.cpp Sat May 31 21:35:01 2003
@@ -7,96 +7,44 @@
//
//===----------------------------------------------------------------------===//
+#include "llvm/Reoptimizer/BinInterface/LLVMTrace.h"
+#include "llvm/Reoptimizer/BinInterface/sparc9.h"
+#include "llvm/Reoptimizer/BinInterface/analyze.h"
+#include "llvm/Reoptimizer/BinInterface/sparcdis.h"
+#include "llvm/Reoptimizer/BinInterface/bitmath.h"
+#include "llvm/Reoptimizer/BinInterface/sparcbin.h"
+#include "llvm/Reoptimizer/Mapping/LLVMinfo.h"
+#include "llvm/Reoptimizer/GetTraceTime.h"
#include "llvm/Reoptimizer/TraceCache.h"
#include "llvm/Reoptimizer/VirtualMem.h"
#include "llvm/Reoptimizer/InstrUtils.h"
-#include "llvm/Reoptimizer/GetTraceTime.h"
-#include "llvm/Reoptimizer/Mapping/LLVMinfo.h"
#include "llvm/Bytecode/Reader.h"
#include "llvm/Module.h"
#include "llvm/iTerminators.h"
+#include "llvm/iOther.h"
+#include "llvm/iPHINode.h"
+#include "llvm/iMemory.h"
#include "llvm/Support/CFG.h"
#include "TriggerAuxillary.h"
#include <iostream>
#include <fstream>
+#include <string>
+#include <algorithm>
using std::vector;
using std::map;
+using std::pair;
extern int llvm_length;
extern const unsigned char LLVMBytecode[];
extern void** llvmFunctionTable[];
-
int reopt_threshold;
-inline Module *initModules(vector<Function *> &funcList){
- Module *M;
-#ifdef READER_TIME
- cpc_count_usr_events(1);
-#endif
- //BytecodeParser Parser;
- M = ParseBytecodeBuffer(LLVMBytecode, llvm_length);
-#ifdef READER_TIME
- cpc_count_usr_events(0);
-#endif
- assert(M && "Module parsing failed!");
-
- //read in pointers to functions
- int mmn = -1;
- for(Module::iterator MI=M->begin(), ME=M->end(); MI!=ME; MI++){
- Function *F = MI;
-
- if(F->isExternal()) {
- continue;
- }
-
- mmn++;
- funcList.push_back(F);
- }
- return M;
-}
-
-
-bool isThrashing(TraceCache *tr, uint64_t startAddr){
- //Keep count of thrashing, so as to avoid it!
- static std::map<uint64_t, int> thrashing;
-
- if(tr->hasTraceAddr(startAddr) && thrashing[startAddr]<4){
- thrashing[startAddr] += 1;
- tr->removeTrace(startAddr);
- }
- else if(thrashing[startAddr] > 3){
- return true;
- }
- return false;
-}
-
-
-bool isWellFormedLoop(vector<BasicBlock *> &vBB, Function *f){
- if(vBB[0] == &f->front() ||
- isa<ReturnInst>(vBB[vBB.size()-1]->getTerminator())){
- //Found a path starting with root
- return false;
- }
-
- //check if loop is not formed
- TerminatorInst *Tcheck = vBB[vBB.size()-1]->getTerminator();
- BranchInst *Bcheck = cast<BranchInst>(Tcheck);
- if(Bcheck->isConditional()){
- if((vBB[0] != Bcheck->getSuccessor(0)) &&
- (vBB[0] != Bcheck->getSuccessor(1))){
- //std::cerr<<"llvm:: Not a loop!\n";
- return false;
- }
- }
- else{
- if(vBB[0] != Bcheck->getSuccessor(0)){
- //std::cerr<<"llvm:: Not a loop!\n";
- return false;
- }
- }
- return true;
-}
+//#define FOR_DEBUG
+void optimizationPasses(Function *F, vector<BasicBlock *> &vBB,
+ LLVMTrace <race, BinInterface &bin,
+ unsigned int totalSections,
+ unsigned int totalInstructions);
extern "C" void trigger(int mn, int pn, int *cnt, int *reg){
static bool initialized = false; //so module is read just once
@@ -105,6 +53,10 @@
static VirtualMem *vm = new VirtualMem();
static TraceCache *tr = new TraceCache();
+ static BinInterface bin(1024*1024, vm, tr); //allocate 1mb
+
+
+ bin.clear();
#ifdef GET_TRIGGER_TIME
llvm_trigger_time_start();
@@ -112,6 +64,9 @@
if(!initialized){
M = initModules(funcList);
+#ifdef FOR_DEBUG
+ std::cerr<<M;
+#endif
initialized = true;
}
@@ -119,231 +74,267 @@
assert(funcList[mn] && "Function not parsed!");
-
- ///Do analysis over module
- vector<Instruction *> instToRemv;
-
- findAllRegs(funcList[mn], instToRemv);
-
- std::map<uint64_t, char> addrToRm;
- //addrToRm[0x000000] = 1;
-
- for(std::vector<Instruction *>::iterator IRI = instToRemv.begin(), IRE =
- instToRemv.end(); IRI != IRE; ++IRI){
- std::vector<uint64_t> vaddr = getLLVMInstrInfo(*IRI);
- for(std::vector<uint64_t>::iterator VRR = vaddr.begin(), VRRE = vaddr.end();
- VRR != VRRE; ++VRR){
- if(!isBranchInstr(vm->readInstrFrmVm(*VRR, tr)))
- addrToRm[*VRR] = 3;
- }
- }
-
std::vector<BasicBlock *> vBB; //trace of BBs
- // std::vector<Instruction *> instToErase;
-
-
-#ifdef BBTRACE_TIME
- cpc_count_usr_events(1);
-#endif
getBBtrace(vBB, pn, funcList[mn]);//, instToErase);
-#ifdef BBTRACE_TIME
- cpc_count_usr_events(0);
-#endif
-
if(!isWellFormedLoop(vBB, funcList[mn])){
cnt[pn] = -99999999;
-#ifdef GET_TRIGGER_TIME
- llvm_trigger_time_end();
-#endif
return;
}
-#ifdef MAP_TIME
- cpc_count_usr_events(1);
-#endif
- std::pair<uint64_t, uint64_t> firtBBLimits =
+ std::pair<uint64_t, uint64_t> firstBBLimits =
getBasicBlockInfo(*(vBB.begin()));
-#ifdef MAP_TIME
- cpc_count_usr_events(0);
-#endif
- uint64_t startAddr = firtBBLimits.first;
+
+ uint64_t startAddr = firstBBLimits.first;
assert(startAddr && "startAddr should have been defined!");
//return if SAME trace already there!
if(tr->hasTraceAddr(startAddr) && tr->hasTraceId(pn)){
- //std::cerr<<"Trace exists!!!\n";
-#ifdef GET_TRIGGER_TIME
- llvm_trigger_time_end();
-#endif
cnt[pn] = -9999999;
return;
}
-
-
+ /*
if(isThrashing(tr, startAddr)){
-#ifdef GET_TRIGGER_TIME
- llvm_trigger_time_end();
-#endif
cnt[pn] = -9999999;
return;
}
+ */
-
- //the trace of instructions
- vector<unsigned int> trace;
-
- //map of call instructions
- std::map<int, uint64_t> callMap;
+ cnt[pn] = -9999999;
+
+ //map of cids to target for which branch condition is to be reverse
+ map<unsigned int, uint64_t> toReverse;
+
+ //map of cids for which branch dest is to be fixed
+ map<unsigned int, uint64_t> toFixCid; //cid, original PC
- //branch target map!
- std::map<int, uint64_t> targetMap;
+ //cid of BA to top
+ unsigned cidToTop;
- //map of branches
- std::map<int, int> branchMap; //branch at index, was located at PC
- int instIndex = 0;
+ //map of BB to starting cid
+ map<BasicBlock *, unsigned int> bbToCid;
+
+ //Basic block to the epilog section
+ //the BB branches out to
+ map<BasicBlock *, unsigned int> bbToSec;
+
- //Now iterate ove trace of BBs, and insert them into the cache
+ //map of BBs whose unconditional or branch has been removed
+ map<BasicBlock *, unsigned char> removedBranch;
+ const unsigned char unCondBr = UNCOND_BR, condBr = CONDBR;
+#ifdef FOR_DEBUG
+ printTrace(vBB, pn);
+#endif
+ unsigned int secId = SECTION_TRACE+1;
+
+ unsigned int unrollCount = 1; //the loop unroll counter
+ unsigned startCID = 0;
+ unsigned cidOffset = 0;
- int branchIndex = 0;
- map<int, vector<unsigned int> *> exitStubs;
- vector<unsigned int> *stubVec = new vector<unsigned int>();
+ bool resetLoop = false;
+ //Now iterate ove trace of BBs, and insert them into the cache
for(vector<BasicBlock *>::iterator VBI = vBB.begin(), VBE = vBB.end();
VBI!=VBE; ++VBI){
+ if(resetLoop){
+ VBI = vBB.begin();
+ resetLoop = false;
+ }
+
//Take the first instr of the basic block, and insert
//all instructions uptil the end of basic block in the trace
-#ifdef MAP_TIME
- cpc_count_usr_events(1);
-#endif
+
std::pair<uint64_t, uint64_t> bbInst = getBasicBlockInfo(*VBI);
-#ifdef MAP_TIME
- cpc_count_usr_events(0);
-#endif
uint64_t bbStart = bbInst.first;
uint64_t bbEnd = bbInst.second;
+#ifdef FOR_DEBUG
+ std::cerr<<"Start: "<<bbStart<<"\t End: "<<bbEnd<<"\n";
+#endif
+ //get the instructions until which to insert
+ uint64_t startBB = bbStart;
- //std::cerr<<"Start: "<<(void *)bbStart<<"\t End: "<<(void *)bbEnd<<"\n";
-
- for(uint64_t addr = bbStart; addr <= bbEnd; addr+=4){
- unsigned instr = vm->readInstrFrmVm(addr, tr);
+ bool breakLoop = false;
- if(addrToRm.find(addr) != addrToRm.end()){
- if(!isCallInstr(instr))
- stubVec->push_back(instr);
- continue;
- }
+ for(uint64_t addr = bbStart; !breakLoop && addr <= bbEnd; addr+=4){
+ unsigned instr = vm->readInstrFrmVm(addr, tr);
assert(instr);
-
- bool gotoNextBB = false;
+
+ unsigned int cid;
if(isBranchInstr(instr) && !isBranchNever(instr)){
+ cid = bin.insert(SECTION_TRACE, (uint *)(intptr_t)startBB,
+ (uint *)(intptr_t)addr);
+
+ if(unrollCount == 1 && startBB != addr){
+ bbToCid[*VBI] = cid;
+ bbToSec[*VBI] = secId;
+ if(!startCID)
+ startCID = cid;
+ }
+
+ unsigned instIndex = ((addr-startBB)/4); //instructions
+ startBB = getBranchTarget(instr, addr);
+
if(isBranchAlways(instr)){
//check that the target of branch is next in trace!
- if(VBI != VBE-1){//is not last BB
+ if(VBI != VBE-1 ||
+ ((VBI == VBE-1) && unrollCount < UNROLL_FACTOR)){//is not last BB
TerminatorInst *TI = (*VBI)->getTerminator();
BranchInst *BI = cast<BranchInst>(TI);
- assert(BI &&
- getBasicBlockInfo(BI->getSuccessor(0)).first ==
- getBranchTarget(instr, addr) && "Incorrect trace!");
- //insert delay slot
- if(addrToRm.find(addr+4) == addrToRm.end())
- trace.push_back(vm->readInstrFrmVm(addr+4, tr));
- else{
- stubVec->push_back(vm->readInstrFrmVm(addr+4, tr));
- trace.push_back(NOP);
- }
+ if(!BI->isConditional())
+ assert(BI &&
+ getBasicBlockInfo(BI->getSuccessor(0)).first ==
+ getBranchTarget(instr, addr) && "Incorrect trace!");
+ else
+ assert(BI &&
+ (getBasicBlockInfo(BI->getSuccessor(0)).first ==
+ getBranchTarget(instr, addr)
+ || getBasicBlockInfo(BI->getSuccessor(1)).first ==
+ getBranchTarget(instr, addr))
+ && "Incorrect trace!");
+ //removed a branch
+ removedBranch[*VBI] = unCondBr;
+ //delay slot
+ unsigned int dscid = bin.insert(SECTION_TRACE,
+ (uint *)(intptr_t)(addr+4),
+ (uint *)(intptr_t)(addr+8));
+ if(unrollCount == 1 && !bbToCid[*VBI]){
+ bbToCid[*VBI] = dscid;
+ bbToSec[*VBI] = secId;
+ if(!startCID)
+ startCID = dscid;
+ }
+
+ if((VBI == VBE-1) && unrollCount < UNROLL_FACTOR){
+
+ if(unrollCount == 1)
+ cidOffset = (bbToCid[*VBI]+instIndex) - startCID + 1;
+
+ unrollCount++;
+
+ VBI = vBB.begin();
+ resetLoop = true;
+ }
+
instIndex++;
- addr += 4;
+ breakLoop = true; //Nothing else in this BB to enter
}
else{
- //else must be last BB, so just ignore branch and insert a BA to top
+ //else must be last BB, so just ignore branch and insert a BA to top
TerminatorInst *TI = (*VBI)->getTerminator();
BranchInst *BI = cast<BranchInst>(TI);
assert(BI &&
getBasicBlockInfo(BI->getSuccessor(0)).first == startAddr
&& "Incorrect trace");
- //insert a BA going to the top
- trace.push_back(getBranchInst
- (0x10800000,
- (uint64_t)(intptr_t)&trace[0],
- (uint64_t)(intptr_t)&trace[instIndex]));
- //insert delay slot
- if(addrToRm.find(addr+4) == addrToRm.end())
- trace.push_back(vm->readInstrFrmVm(addr+4, tr));
- else{
- stubVec->push_back(vm->readInstrFrmVm(addr+4, tr));
- trace.push_back(NOP);
- }
-
- exitStubs[branchIndex] = stubVec;
- branchIndex++;
- stubVec = new vector<unsigned int>();
+ //later change this to BA
+ cidToTop = cid + instIndex-1;
+ unsigned int dscid = bin.insert(SECTION_TRACE,
+ (uint *)(intptr_t)(addr+4),
+ (uint *)(intptr_t)(addr+8));
+ if(unrollCount == 1 && !bbToCid[*VBI]){
+ bbToCid[*VBI] = dscid;
+ bbToSec[*VBI] = secId;
+ if(!startCID)
+ startCID = dscid;
+ }
+ instIndex += 1;
- instIndex += 2;
- addr += 4;
+ removedBranch[*VBI] = unCondBr;
+ breakLoop = true;
}
- gotoNextBB = true;
}
else{ //is a conditional branch!
+
if(VBI != VBE-1){//is not last BB
//check if it points to next BB insequence
- //TerminatorInst *TI = (*(VBI+1))->getTerminator();
- //BranchInst *BI = cast<BranchInst>(TI);
- //assert(BI && "No branch???");
uint64_t nextBBaddr = getBasicBlockInfo(*(VBI+1)).first;
uint64_t tar = getBranchTarget(instr, addr);
if(tar == nextBBaddr){
//taken path
//reverse the branch condition, and point it to addr+8
- unsigned int revBr = vm->getInvertedBranch(instr);
- targetMap[instIndex] = addr+8;
-
- trace.push_back(revBr);
- if(addrToRm.find(addr+4) == addrToRm.end())
- trace.push_back(vm->readInstrFrmVm(addr+4, tr));
- else{
- stubVec->push_back(vm->readInstrFrmVm(addr+4, tr));
- trace.push_back(NOP);
- }
-
- exitStubs[branchIndex] = stubVec;
- branchIndex++;
- stubVec = new vector<unsigned int>();
+ //hoist the DS above the branch
+ unsigned int br = vm->readInstrFrmVm(addr, tr);
+ unsigned int ds = vm->readInstrFrmVm(addr+4, tr);
+ //check if DS writes into reg used by branch
+ unsigned int flags_br = sparc_analyze(br);
+ if(flags_br & IF_R_RS1){
+ unsigned int flags_ds = sparc_analyze(ds);
+ if(flags_ds & IF_W_RD){
+ assert(((RD_FLD(ds, INSTR_RD)) !=(RD_FLD(br, INSTR_RS1)))
+ && "Can not move delay slot above branch!");
+ }
+ }
+
+ //unsigned int dscid = bin.insert(SECTION_TRACE, (uint *)addr+4,
+ // (uint *)(addr+8));
+ //bin.insert(SECTION_TRACE, (uint *)addr, (uint *)(addr+4));
+
+ unsigned int dscid =
+ bin.insert(SECTION_TRACE, (uint *)(intptr_t)addr,
+ (uint *)(intptr_t)(addr+8));
+
+ if(unrollCount == 1 && !bbToCid[*VBI]){
+ bbToCid[*VBI] = dscid;
+ bbToSec[*VBI] = secId;
+ if(!startCID)
+ startCID = dscid;
+ }
+
+ //get reverse branch
+ toReverse[cid+instIndex]=addr+8;
+ toFixCid[cid+instIndex] = addr;
instIndex += 2;
-
- addr += 8;
- gotoNextBB = true;
+ breakLoop = true;
+ //removedBranch[*VBI] = condBr;
}
else{
//not taken path
//leave the instruction as is, and goto next instruction
- targetMap[instIndex] = getBranchTarget(instr, addr);
-
- trace.push_back(instr);
- if(addrToRm.find(addr+4) == addrToRm.end())
- trace.push_back(vm->readInstrFrmVm(addr+4, tr));
- else{
- stubVec->push_back(vm->readInstrFrmVm(addr+4, tr));
- trace.push_back(NOP);
- }
-
- exitStubs[branchIndex] = stubVec;
- branchIndex++;
- stubVec = new vector<unsigned int>();
-
- instIndex += 2;
- addr += 8;
+ //hoist the DS above the branch
+ unsigned int br = vm->readInstrFrmVm(addr, tr);
+ unsigned int ds = vm->readInstrFrmVm(addr+4, tr);
+ //check if DS writes into reg used by branch
+ unsigned int flags_br = sparc_analyze(br);
+ if(flags_br & IF_R_RS1){
+ unsigned int flags_ds = sparc_analyze(ds);
+ if(flags_ds & IF_W_RD){
+ assert(((RD_FLD(ds, INSTR_RD)) !=(RD_FLD(br, INSTR_RS1)))
+ && "Can not move delay slot above branch!");
+ }
+ }
+
+ //unsigned int dscid = bin.insert(SECTION_TRACE, (uint *)addr+4,
+ // (uint *)(addr+8));
+ //bin.insert(SECTION_TRACE, (uint *)addr, (uint *)(addr+4));
+
+ unsigned int dscid = bin.insert(SECTION_TRACE,
+ (uint *)(intptr_t)addr,
+ (uint *)(intptr_t)(addr+8));
+
+ if(unrollCount == 1 && !bbToCid[*VBI]){
+ bbToCid[*VBI] = dscid;
+ bbToSec[*VBI] = secId;
+ if(!startCID)
+ startCID = dscid;
+ }
+
+ toFixCid[cid+instIndex] = addr;
+ startBB = addr+8;
+ addr += 4;
+ //removedBranch[*VBI] = condBr;
+ instIndex += 2; //MARK
}
+ if(unrollCount == 1)
+ secId++;
}
else{ // last BB in seq!
TerminatorInst *TI = (*VBI)->getTerminator();
@@ -352,177 +343,140 @@
getBasicBlockInfo(BI->getSuccessor(1)).first == startAddr
&& "Incorrect trace");
- //insert a BA going to the top
- trace.push_back(getBranchInst
- (0x10800000,
- (uint64_t)(intptr_t)&trace[0],
- (uint64_t)(intptr_t)&trace[instIndex]));
-
-
-
- //exitStubs[branchIndex] = stubVec;
- //branchIndex++;
- stubVec = new vector<unsigned int>();
-
- if(addrToRm.find(addr+4) == addrToRm.end())
- trace.push_back(vm->readInstrFrmVm(addr+4, tr));
- else{
- stubVec->push_back(vm->readInstrFrmVm(addr+4, tr));
- trace.push_back(NOP);
- }
-
- vector<unsigned int> *tVec = exitStubs[branchIndex-1];
- assert(tVec);
-
- for(vector<unsigned int>::iterator TVI = stubVec->begin(),
- TVE = stubVec->end(); TVI != TVE; ++TVI)
- tVec->push_back(*TVI);
-
- instIndex += 2;
-
- addr += 4;
- gotoNextBB = true;
+ cidToTop = cid + instIndex-1;
+ unsigned int dscid = bin.insert(SECTION_TRACE,
+ (uint *)(intptr_t)(addr+4),
+ (uint *)(intptr_t)(addr+8));
+ if(unrollCount == 1 && !bbToCid[*VBI]){
+ bbToCid[*VBI] = dscid;
+ bbToSec[*VBI] = secId;
+ if(!startCID)
+ startCID = dscid;
+ }
+
+ if(unrollCount < UNROLL_FACTOR){
+
+ if(unrollCount == 1){
+ cidOffset = (bbToCid[*VBI]+instIndex) - startCID + 1;
+ }
+
+ unrollCount++;
+ VBI = vBB.begin();
+ resetLoop = true;
+ }
+
+ removedBranch[*VBI] = condBr;
+ instIndex += 1;
+ breakLoop = true;
}
}
}
-
- else if(isCallInstr(instr)){
- callMap[instIndex] = getCallTarget(instr, addr);
-
- trace.push_back(instr);
- instIndex++;
- }
-
- else{
- trace.push_back(instr);
- instIndex++;
- }
-
- if(gotoNextBB)
- break;
}
}
-
- //insert exit code!
- getBranchExitCode(trace, branchMap, targetMap, callMap, exitStubs);
- //Now add trace to cache, and we are all set!
- vector<unsigned int> *vstubs = exitStubs[branchIndex-1];
+
+ //secId is last epilog number+1
+
+ //get cids of instructions live out
+ vector<unsigned int> liveOut;
+
+ //get cids of pinned instructions
+ vector<unsigned int> pinned;
+
+ LLVMTrace ltrace(&bin, vm, tr);
+ ltrace.addTrace(bbToCid, bbToSec, removedBranch, secId-1, cidOffset,
+ UNROLL_FACTOR);
+
+ //getLiveOut(liveOut, vBB, bbToCid, removedBranch, vm, tr, bin);
+ getPinned(pinned, vBB, bbToCid, removedBranch, vm, tr);//, cidOffset);//,
+ // UNROLL_FACTOR);
+
+ //form SSA ids
+ bin.complete();
+
+ //mark instructions liveout
/*
- if(vstubs){
- if(!tr->addTrace(startAddr, trace, pn, callMap, branchMap, vstubs))
- std::cerr<<" Trace could not be added!!!\n";
+ for(vector<unsigned int>::iterator VI = liveOut.begin(), VE = liveOut.end();
+ VI != VE; ++VI)
+ bin.liveout(*VI);
+ */
+
+ //for each toReverse, reverse the opcode
+ for(map<unsigned int, uint64_t>::iterator VI = toReverse.begin(),
+ VE = toReverse.end(); VI != VE; ++VI){
+ bin.reverseBranch(VI->first);
+ //bin.setBranchDest(*VI, (unsigned int *)(toFixCid[*VI]+8));
}
- else*/
-
- if(!tr->addTrace(startAddr, trace, pn, callMap, branchMap))
- std::cerr<<" Trace could not be added!!!\n";
+ //map of epilog and abs address
+ map<unsigned int, uint64_t> epToAbsAddr;
-#ifdef GET_TRIGGER_TIME
- llvm_trigger_time_end();
-#endif
-}
+ //for each cidToFix, insert an epilogue and insert a BA in the epilogue
+ for(map<unsigned int, uint64_t>::iterator MI = toFixCid.begin(),
+ ME = toFixCid.end(); MI != ME; ++MI){
+ unsigned int epilog = bin.newepilog();
+ bin.setBranchAsInternal(MI->first, epilog);
+ unsigned nop = bin.newnop();
+ bin.move(nop, MI->first);
+ bin.move_instr_before(MI->first+1, MI->first);
-void getBranchExitCode(vector<unsigned int> &instVec,
- map<int, int> &branchMap,
- map<int, uint64_t> &targetMap,
- map<int, uint64_t> &callMap,
- map<int, vector<unsigned int> *> exitStubs){
-
- //for each branch, insert code!
- int instIndex = instVec.size();
+ if(!toReverse[MI->first])
+ epToAbsAddr[epilog] = getBranchTarget(vm->readInstrFrmVm(MI->second, tr),
+ MI->second);
+ else
+ epToAbsAddr[epilog] = toReverse[MI->first];
+ }
+
+
+ //insert a BA going to the top
+ unsigned int newBr = bin.newbranch(MK_INSTR_BRANCH_NO_RS1(COND_BA),
+ SECTION_TRACE);
- int branchIndex = 0;
- for(map<int, uint64_t>::iterator MI = targetMap.begin(), ME = targetMap.end();
- MI != ME; ++MI, branchIndex++){
+ //std::cerr<<"Cid to to "<<cidToTop<<"\n";
+ unsigned nop = bin.newnop();
+ bin.move(nop, cidToTop);
+ bin.move(newBr, nop);
- assert(exitStubs[branchIndex]);
+ bin.reduce();
- unsigned int instr = instVec[MI->first];
- uint64_t pc = MI->second;
-
-#ifdef GET_TRACE_TIME
- instVec.push_back(0);//just dummy, so we can use its adress
+ //mark instructions as pinned
+ for(int i = 0; i < UNROLL_FACTOR; i++){
+ for(vector<unsigned int>::iterator VI = pinned.begin(), VE = pinned.end();
+ VI != VE; ++VI)
+ bin.pinDown(*VI + (cidOffset*i));
+ }
- //call llvm_time_end
- unsigned int call_inst = getCallInstr((uint64_t)&llvm_time_end,
- (uint64_t)&instVec[instIndex]);
- instVec[instIndex] = call_inst;
+ //now insert branches in epilogs
+ for(map<unsigned int, uint64_t>::iterator MI = epToAbsAddr.begin(),
+ ME = epToAbsAddr.end(); MI != ME; ++MI){
- callMap[instIndex] = (uint64_t)&llvm_time_end;//CHANGED! instVec[instIndex];
- //end call_inst!
+ bin.assignRetAdress(MI->first, (uint *)(intptr_t)MI->second);
+#ifdef FOR_DEBUG
+ std::cerr<<"------- Section "<<MI->first<<"\n";
+ bin.print(MI->first);
+ std::cerr<<"--------------------\n";
#endif
+ }
- //insert instructions in exit stub
- vector<unsigned int> *stubVec = exitStubs[branchIndex];
- for(vector<unsigned int>::iterator VI = stubVec->begin(),
- VE = stubVec->end(); VI != VE; ++VI)
- instVec.push_back(*VI);
-
-
- //save %io, ad1
- unsigned int stx1 = 0xf077a000|0x7f7; //stx %i0, %fp+offset-8
- unsigned int stx2 = 0xf277a000|0x7ef; //stx %i1, offset-16
-
- //sethi
- uint64_t target = targetMap[MI->first];
-
- unsigned int r1 = ((target>>32)&(0xfffff000))>>10;
- unsigned int r2 = (target>>32)&(0xfff);
- unsigned int sethi1 = 0x31000000 | r1;
-
- //or %i0, r2, %i0
- unsigned int or1 = 0xb0162000|r2;
-
- //sllx %i0, 32, %i1
- unsigned int sllx = 0xb32e3020;
-
- //sethi2
- unsigned int r11 = ((target)&(0xfffff000))>>10;
- unsigned int r22 = (target)&(0xfff);
- unsigned int sethi2 = 0x31000000 | r11;
-
- //or %i0, r22, %i0
- unsigned int or2 = 0xb0162000|r22;
-
- //add %i0, %i1, %i0
- unsigned int add = 0xb0064018;
-
- //load ad1, %i0
- unsigned load1 = 0xf05fa000|0x7f7;
- //load ad2, %i1
- unsigned load2 = 0xf25fa000|0x7ef;
-
- //jumpl %i0
- unsigned int jmpl = 0x81c62000;
-
- //insert instructions into instVec
- instVec.push_back(stx1);
- instVec.push_back(stx2);
- instVec.push_back(sethi1);
- instVec.push_back(or1);
- instVec.push_back(sllx);
- instVec.push_back(sethi2);
- instVec.push_back(or2);
- instVec.push_back(add);
- instVec.push_back(load2);
- instVec.push_back(jmpl);
- instVec.push_back(load1); //delay slot!
-
- uint64_t newInst = getBranchInst(instr,
- (uint64_t)(intptr_t)&instVec[instIndex],
- (uint64_t)(intptr_t)&instVec[MI->first]);
- instVec[MI->first] = newInst;
-
- //change original call map to point to new PC
- branchMap.erase(MI->first);
- branchMap[MI->first] = instIndex;
+ optimizationPasses(funcList[mn], vBB, ltrace, bin, secId, cidOffset);
- instIndex += (11 + stubVec->size());
+#ifdef FOR_DEBUG
+ for(unsigned int i = 0; i < 2+(secId-2)*UNROLL_FACTOR; i++){
+ std::cerr<<"------------SECTION "<<i<<"\n";
+ bin.print(i);
+ }
+ std::cerr<<"-------------------------\n";
+#endif
-#ifdef GET_TRACE_TIME
- instIndex++;
+ uint64_t addrToOutput;
+
+ if(!tr->addTrace(startAddr, bin.predict()/4, pn, addrToOutput))
+ std::cerr<<" Trace could not be added!!!\n";
+
+ bin.emit((unsigned char *)(intptr_t)addrToOutput);
+
+ doFlush(addrToOutput-4, addrToOutput+bin.predict()/4);
+#ifdef FOR_DEBUG
+ std::cerr<<"-----------\n";
#endif
- }
}
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