[llvm-commits] CVS: llvm/include/llvm/Reoptimizer/BinInterface/analyze.h

[Anand Shukla]

Changes in directory llvm/include/llvm/Reoptimizer/BinInterface:

analyze.h added (r1.1)

---
Log message:

First version of working bininterface API/implementation

---
Diffs of the changes:

Index: llvm/include/llvm/Reoptimizer/BinInterface/analyze.h
diff -c /dev/null llvm/include/llvm/Reoptimizer/BinInterface/analyze.h:1.1
*** /dev/null	Sat May 31 17:10:32 2003
--- llvm/include/llvm/Reoptimizer/BinInterface/analyze.h	Sat May 31 17:10:21 2003
***************
*** 0 ****
--- 1,70 ----
+ //===--------llvm/Reoptimizer/BinInterface/analyze.h--------------*- C++ -*--=//
+ //
+ //  Analysis API
+ //
+ //  * Initial implementation
+ //  * Fixed API to handle the special case where RD can be read from
+ //  * Extended API to handle register read/write to G0 differently
+ //
+ //  TODO:
+ //  * Floating point support is lacking
+ //  * Verify all instructions are supported (double check disasm tool too)
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef __ANALYZE__
+ #define __ANALYZE__
+ 
+ #include "sparcpriv.h"
+ 
+ #define IF_RS1   0x001			// Presence of RS1 field in instruction
+ #define IF_RS2   0x002			// Presence of RS2 field in instruction
+ #define IF_RD    0x004   		// Presence of RD field in instruction
+ #define IF_BR    0x008			// BRANCH
+ #define IF_WCC   0x010			// write to condition code
+ #define IF_RCC   0x020			// read from condition code
+ #define IF_W_RD  0x040     // instruction writes rd
+ #define IF_R_RD  0x080     // instruction reads rd (not exclusive with above)
+ #define IF_R_RS1 0x100     // reads from RS1
+ #define IF_R_RS2 0x200     // reads from RS2
+ #define IF_CALL  0x400     // Is call instruction? (affects live registers)
+ #define IF_USR   0x800     // Later in the code we wish to be able to pack other
+ //  flags along side these when we store them in the
+ //  SSA form.  This is the first 'user' flag available
+ 
+ #define IF_RS1_RS2_DEFINED IF_USR //for adding one ALU instruction
+ 
+ 
+ 
+ 
+ /*
+     Important NOTE!
+     
+     Since sparc treats register 0 specially - in such a way that
+     we wish to ignore writes or reads from this register for dataflow
+     analysis.  IF_RS1, IF_RS2, and IF_RD are set independantly of whether
+     their respective register is 0 HOWEVER the read/write flags before are
+     turned off if their respective register is 0.
+ 
+ */
+ 
+ //check if its a floating point instruction
+ //a floating point branch is being handled as an integer branch
+ //since no special handling is done for condition codes
+ bool isFloatingPoint(unsigned instr); 
+ 
+ // parse instruction and return IF flags
+ unsigned sparc_analyze(unsigned instr);
+ 
+ // use these command to expand the information return by analyze
+ unsigned sparc_getwrites(unsigned mask, unsigned instr);
+ unsigned sparc_getreads (unsigned mask, unsigned instr);
+ 
+ // returns a bitmask containing RCC or WCC
+ unsigned sparc_getcc    (unsigned mask, unsigned instr); 
+ 
+ unsigned sparc_setbrdest(unsigned instr, signed reladdr);
+ signed sparc_getbrdest(unsigned instr);
+ 
+ #endif
+