[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/analyze.cpp
Anand Shukla
ashukla at cs.uiuc.edu
Sat May 31 17:08:34 PDT 2003
Changes in directory llvm/lib/Reoptimizer/BinInterface:
analyze.cpp updated: 1.8 -> 1.9
---
Log message:
First version of working bininterface API/implementation
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/BinInterface/analyze.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.8 llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.9
--- llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.8 Thu Apr 10 18:12:35 2003
+++ llvm/lib/Reoptimizer/BinInterface/analyze.cpp Sat May 31 17:07:33 2003
@@ -1,5 +1,4 @@
-//*****************************************************************************
-// SPARC Instruction Analysis
+//===--------llvm/Reoptimizer/BinInterface/analyze.cpp------------*- C++ -*--=//
//
// Analysis API Implementation
//
@@ -11,15 +10,13 @@
// * Floating point support is lacking
// * Verify all instructions are supported (double check disasm tool too)
//
-// 2002 Cameron Buschardt
-//*****************************************************************************
+//===----------------------------------------------------------------------===//
+#include "llvm/Reoptimizer/BinInterface/analyze.h" // SPARC analysis library
+#include "llvm/Reoptimizer/BinInterface/bitmath.h" // binary math routines
+#include "llvm/Reoptimizer/BinInterface/sparc9.h" // SPARC9 opcode definitions
#include <stdio.h>
#include <stdlib.h>
-
-#include "llvm/Reoptimizer/BinInterface/sparc9.h" // SPARC 9 opcode and field definitions
-#include "llvm/Reoptimizer/BinInterface/bitmath.h" // Binary arithmetic library
-#include "analyze.h" // Defintion of analysis interface
#include <assert.h>
//*****************************************************************************
@@ -34,19 +31,77 @@
//
//*****************************************************************************
+bool isFloatingPoint(unsigned instr){
+ if(RD_FLD(instr,INSTR_OP)==OP_2 && RD_FLD(instr, INSTR_OP3) == OP3_FPU){
+ switch(RD_FLD(instr, INSTR_OP3)){
+ case OPF_FsTOx:
+ case OPF_FsTOi:
+ case OPF_FsTOd:
+ case OPF_FsTOq:
+ case OPF_FdTOx:
+ case OPF_FdTOi:
+ case OPF_FdTOs:
+ case OPF_FdTOq:
+ case OPF_FqTOd:
+ case OPF_FqTOi:
+ case OPF_FqTOx:
+ case OPF_FqTOs:
+ case OPF_FxTOt:
+ case OPF_FiTOt:
+ case OPF_FsMULd:
+ case OPF_FdMULq:
+ assert(0 && "instruction not handled");
+ default:
+ return true;
+ }
+ }
+ if(RD_FLD(instr,INSTR_OP)==OP_3){
+ switch(RD_FLD(instr, INSTR_OP3)){
+ case 32:
+ case 33:
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ case 38:
+ case 39:
+ case 48:
+ case 50:
+ case 51:
+ case 52:
+ case 54:
+ case 55:
+ return true;
+ default:
+ return false;
+ }
+ }
+ return false;
+}
+
unsigned sparc_analyzebr(unsigned instr)
{
+ if(RD_FLD(instr, INSTR_OP)==OP_CALL)
+ return IF_BR;
// look at the OP2 field
if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
{
// The sethi instruction zeroes the register
// and loads the immediate into bits 10->31
if (RD_FLD(instr, INSTR_RD) == 0)
- return 0; // This is the special encoding for NOP
+ return 0; // This is the special encoding for NOP
else
return IF_RD | IF_W_RD;
}
- else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
+ else if(RD_FLD(instr, INSTR_OP2)==OP2_FBP ||
+ RD_FLD(instr, INSTR_OP2)==OP2_FBP){
+ return IF_BR;
+ //TODO: IF_FCC???
+ }
+ // else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
+ //--Anand
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC ||
+ RD_FLD(instr, INSTR_OP2)==OP2_BPICC )
{
// Branch on integer condition code
return IF_RCC | IF_BR;
@@ -54,7 +109,9 @@
else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
{
// Branch on integer register with prediction
- return IF_RCC | IF_RS1 | IF_R_RS1;
+ //---Anand
+ //return IF_RCC | IF_RS1 | IF_R_RS1;
+ return IF_BR | IF_RCC | IF_RS1 | IF_R_RS1;
}
else{
// There are a few opcodes missing from this field,
@@ -141,14 +198,16 @@
case OP3_SUBcc:
case OP3_XORcc:
if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_W_RD | IF_R_RS1 | IF_R_RS2;
+ return (IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_W_RD | IF_R_RS1 |
+ IF_R_RS2);
else
return IF_RD | IF_RS1 | IF_WCC | IF_W_RD | IF_R_RS1;
case OP3_ADDCcc:
case OP3_SUBCcc:
if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC | IF_W_RD | IF_R_RS1 | IF_R_RS2;
+ return (IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC | IF_W_RD |
+ IF_R_RS1 | IF_R_RS2);
else
return IF_RD | IF_RS1 | IF_WCC | IF_RCC | IF_W_RD | IF_R_RS1;
@@ -253,7 +312,9 @@
return sparc_analyze_c2(instr);
else if (RD_FLD(instr,INSTR_OP)==OP_3)
return sparc_analyze3(instr);
- else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+ //added call --Anand
+ else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH ||
+ RD_FLD(instr, INSTR_OP)==OP_CALL)
return sparc_analyzebr(instr);
else
return IF_CALL; // Call instruction not seen as branch
@@ -368,24 +429,24 @@
{
if (RD_FLD(instr, INSTR_OP)==OP_CALL)
return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP30),30);
- else
- {
- assert(RD_FLD(instr,INSTR_OP)==OP_BRANCH);
- switch(RD_FLD(instr, INSTR_OP2))
- {
- case OP2_BPR: // D16LO/D16HI
- return SIGN_EXTEND(RD_D16(instr), 16);
- case OP2_BICC: // DISP22 field
- case OP2_FB: // DISP22 field
- return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP22), 22);
- case OP2_FBP: // DISP19 field
- case OP2_BPICC: // DISP19 field
- return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP19), 19);
- default:
- assert(0);
- }
-
+ else{
+ assert(RD_FLD(instr,INSTR_OP)==OP_BRANCH);
+ switch(RD_FLD(instr, INSTR_OP2)){
+ case OP2_BPR: // D16LO/D16HI
+ return SIGN_EXTEND(RD_D16(instr), 16);
+ case OP2_BICC: // DISP22 field
+ case OP2_FB: // DISP22 field
+ return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP22), 22);
+ case OP2_FBP: // DISP19 field
+ case OP2_BPICC: // DISP19 field
+ return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP19), 19);
+ default:
+ assert(0);
+ }
}
+ //will never be here
+ assert(0);
+ return 0;
}
//*****************************************************************************
@@ -424,5 +485,8 @@
assert(0);
}
}
+ //will never be here!
+ assert(0);
+ return 0;
}
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