[llvm-commits] CVS: llvm/lib/Target/Sparc/Makefile SparcV9_F3.td

[Brian Gaeke]

Changes in directory llvm/lib/Target/Sparc:

Makefile updated: 1.19 -> 1.20
SparcV9_F3.td updated: 1.1 -> 1.2

---
Log message:

Makefile: Make SparcV9CodeEmitter.inc depend on SparcV9_F*.td as well. 
SparcV9_F3.td: F3_12 and F3_13 instructions have rd and rs1 fields. Also,
 their fields were totally screwed up. This seems to fix the problem.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/Makefile
diff -u llvm/lib/Target/Sparc/Makefile:1.19 llvm/lib/Target/Sparc/Makefile:1.20
--- llvm/lib/Target/Sparc/Makefile:1.19	Thu May 29 15:09:56 2003
+++ llvm/lib/Target/Sparc/Makefile	Fri May 30 03:02:14 2003
@@ -36,7 +36,7 @@
 
 TEMP_EMITTER_INC = _temp_emitter.inc
 
-SparcV9CodeEmitter.inc: SparcV9.td
+SparcV9CodeEmitter.inc: SparcV9.td SparcV9_F2.td SparcV9_F3.td SparcV9_F4.td SparcV9_Reg.td
 	@echo "TableGen-erating $@"
 	cpp -P SparcV9.td | $(TBLGEN) -gen-emitter > $(TEMP_EMITTER_INC) 
 	mv -f $(TEMP_EMITTER_INC) SparcV9CodeEmitter.inc


Index: llvm/lib/Target/Sparc/SparcV9_F3.td
diff -u llvm/lib/Target/Sparc/SparcV9_F3.td:1.1 llvm/lib/Target/Sparc/SparcV9_F3.td:1.2
--- llvm/lib/Target/Sparc/SparcV9_F3.td:1.1	Wed May 28 22:31:43 2003
+++ llvm/lib/Target/Sparc/SparcV9_F3.td	Fri May 30 03:02:14 2003
@@ -108,9 +108,11 @@
   //set Inst{11-5} = dontcare;
 }
 
-class F3_12<bits<2> opVal, bits<6> op3Val,    string name> : F3 {
+class F3_12<bits<2> opVal, bits<6> op3Val,    string name> : F3_rdrs1 {
   bits<5> shcnt;
 
+  set op  = opVal;
+  set op3 = op3Val;
   set Name = name;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 0; // x field = 0
@@ -118,9 +120,11 @@
   set Inst{4-0} = shcnt;
 }
 
-class F3_13<bits<2> opVal, bits<6> op3Val,    string name> : F3 {
+class F3_13<bits<2> opVal, bits<6> op3Val,    string name> : F3_rdrs1 {
   bits<6> shcnt;
 
+  set op  = opVal;
+  set op3 = op3Val;
   set Name = name;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 1; // x field = 1