[llvm-commits] CVS: llvm/lib/CodeGen/LiveVariables.cpp MachineInstr.cpp PHIElimination.cpp PrologEpilogInserter.cpp RegAllocLocal.cpp RegAllocSimple.cpp
Vikram Adve
vadve at cs.uiuc.edu
Mon May 26 19:06:03 PDT 2003
Changes in directory llvm/lib/CodeGen:
LiveVariables.cpp updated: 1.7 -> 1.8
MachineInstr.cpp updated: 1.70 -> 1.71
PHIElimination.cpp updated: 1.8 -> 1.9
PrologEpilogInserter.cpp updated: 1.10 -> 1.11
RegAllocLocal.cpp updated: 1.15 -> 1.16
RegAllocSimple.cpp updated: 1.38 -> 1.39
---
Log message:
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
---
Diffs of the changes:
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.7 llvm/lib/CodeGen/LiveVariables.cpp:1.8
--- llvm/lib/CodeGen/LiveVariables.cpp:1.7 Mon May 12 09:24:00 2003
+++ llvm/lib/CodeGen/LiveVariables.cpp Mon May 26 19:05:17 2003
@@ -231,7 +231,7 @@
// Process all explicit defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
- if (MO.opIsDef() || MO.opIsDefAndUse()) {
+ if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
if (MO.isVirtualRegister()) {
VarInfo &VRInfo = getVarInfo(MO.getReg());
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.70 llvm/lib/CodeGen/MachineInstr.cpp:1.71
--- llvm/lib/CodeGen/MachineInstr.cpp:1.70 Wed Jan 15 13:47:02 2003
+++ llvm/lib/CodeGen/MachineInstr.cpp Mon May 26 19:05:17 2003
@@ -94,7 +94,7 @@
if (isDefAndUse)
operands[i].flags = MachineOperand::DEFUSEFLAG;
else if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
- operands[i].flags = MachineOperand::DEFFLAG;
+ operands[i].flags = MachineOperand::DEFONLYFLAG;
else
operands[i].flags = 0;
}
@@ -126,7 +126,7 @@
operands[i].regNum = regNum;
if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
- operands[i].flags = MachineOperand::DEFFLAG;
+ operands[i].flags = MachineOperand::DEFONLYFLAG;
else
operands[i].flags = 0;
@@ -152,7 +152,7 @@
// Subsitute operands
for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
if (*O == oldVal)
- if (!defsOnly || O.isDef())
+ if (!defsOnly || !O.isUseOnly())
{
O.getMachineOperand().value = newVal;
++numSubst;
@@ -161,7 +161,7 @@
// Subsitute implicit refs
for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i)
if (getImplicitRef(i) == oldVal)
- if (!defsOnly || implicitRefIsDefined(i))
+ if (!defsOnly || !getImplicitOp(i).opIsUse())
{
getImplicitOp(i).value = newVal;
++numSubst;
@@ -281,7 +281,8 @@
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
- if (getNumOperands() && operandIsDefined(0)) {
+ if (getNumOperands() &&
+ (getOperand(0).opIsDefOnly() || getOperand(0).opIsDefAndUse())) {
::print(getOperand(0), OS, TM);
OS << " = ";
++StartOp; // Don't print this operand again!
@@ -289,14 +290,15 @@
OS << TM.getInstrInfo().getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
+ const MachineOperand& mop = getOperand(i);
if (i != StartOp)
OS << ",";
OS << " ";
- ::print(getOperand(i), OS, TM);
+ ::print(mop, OS, TM);
- if (operandIsDefinedAndUsed(i))
+ if (mop.opIsDefAndUse())
OS << "<def&use>";
- else if (operandIsDefined(i))
+ else if (mop.opIsDefOnly())
OS << "<def>";
}
@@ -305,10 +307,10 @@
OS << "\tImplicitRefs: ";
for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
OS << "\t";
- OutputValue(OS, getImplicitRef(i));
- if (implicitRefIsDefinedAndUsed(i))
+ OutputValue(OS, getImplicitRef(i));
+ if (getImplicitOp(i).opIsDefAndUse())
OS << "<def&use>";
- else if (implicitRefIsDefined(i))
+ else if (getImplicitOp(i).opIsDefOnly())
OS << "<def>";
}
}
@@ -323,9 +325,9 @@
for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
- if (MI.operandIsDefined(i))
+ if (MI.getOperand(i).opIsDefOnly())
os << "<d>";
- if (MI.operandIsDefinedAndUsed(i))
+ if (MI.getOperand(i).opIsDefAndUse())
os << "<d&u>";
}
@@ -335,8 +337,8 @@
os << "\tImplicit: ";
for (unsigned z=0; z < NumOfImpRefs; z++) {
OutputValue(os, MI.getImplicitRef(z));
- if (MI.implicitRefIsDefined(z)) os << "<d>";
- if (MI.implicitRefIsDefinedAndUsed(z)) os << "<d&u>";
+ if (MI.getImplicitOp(z).opIsDefOnly()) os << "<d>";
+ if (MI.getImplicitOp(z).opIsDefAndUse()) os << "<d&u>";
os << "\t";
}
}
Index: llvm/lib/CodeGen/PHIElimination.cpp
diff -u llvm/lib/CodeGen/PHIElimination.cpp:1.8 llvm/lib/CodeGen/PHIElimination.cpp:1.9
--- llvm/lib/CodeGen/PHIElimination.cpp:1.8 Mon May 12 12:37:30 2003
+++ llvm/lib/CodeGen/PHIElimination.cpp Mon May 26 19:05:17 2003
@@ -165,7 +165,7 @@
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
MachineOperand &MO = PrevInst->getOperand(i);
if (MO.isVirtualRegister() && MO.getReg() == IncomingReg)
- if (MO.opIsDef() || MO.opIsDefAndUse()) {
+ if (MO.opIsDefOnly() || MO.opIsDefAndUse()) {
HaveNotEmitted = false;
break;
}
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.10 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.11
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.10 Fri May 2 13:44:42 2003
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Mon May 26 19:05:17 2003
@@ -108,7 +108,8 @@
MachineOperand &MO = (*I)->getOperand(i);
assert(!MO.isVirtualRegister() &&
"Register allocation must be performed!");
- if (MO.isPhysicalRegister() && MO.opIsDef())
+ if (MO.isPhysicalRegister() &&
+ (MO.opIsDefOnly() || MO.opIsDefAndUse()))
ModifiedRegs[MO.getReg()] = true; // Register is modified
}
++I;
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.15 llvm/lib/CodeGen/RegAllocLocal.cpp:1.16
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.15 Sun May 11 22:54:14 2003
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Mon May 26 19:05:17 2003
@@ -489,7 +489,7 @@
// Loop over all of the operands of the instruction, spilling registers that
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if ((MI->getOperand(i).opIsDef() || MI->getOperand(i).opIsDefAndUse()) &&
+ if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) &&
MI->getOperand(i).isPhysicalRegister()) {
unsigned Reg = MI->getOperand(i).getAllocatedRegNum();
spillPhysReg(MBB, I, Reg); // Spill any existing value in the reg
@@ -512,8 +512,8 @@
// we need to scavenge a register.
//
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
- if (MI->getOperand(i).opIsDef() &&
- MI->getOperand(i).isVirtualRegister()) {
+ if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse())
+ && MI->getOperand(i).isVirtualRegister()) {
unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum();
unsigned DestPhysReg;
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.38 llvm/lib/CodeGen/RegAllocSimple.cpp:1.39
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.38 Tue Jan 14 15:58:41 2003
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Mon May 26 19:05:17 2003
@@ -173,7 +173,7 @@
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
- if (op.opIsDef()) {
+ if (op.opIsDefOnly() || op.opIsDefAndUse()) {
if (TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) && i == 0) {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
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