[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrInfo.cpp X86InstrInfo.h

[Misha Brukman]

Changes in directory llvm/lib/Target/X86:

X86InstrInfo.cpp updated: 1.12 -> 1.13
X86InstrInfo.h updated: 1.21 -> 1.22

---
Log message:

Implement the TargetInstrInfo's createNOPinstr() and isNOPinstr() interface.


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Diffs of the changes:

Index: llvm/lib/Target/X86/X86InstrInfo.cpp
diff -u llvm/lib/Target/X86/X86InstrInfo.cpp:1.12 llvm/lib/Target/X86/X86InstrInfo.cpp:1.13
--- llvm/lib/Target/X86/X86InstrInfo.cpp:1.12	Tue Jan 14 15:59:16 2003
+++ llvm/lib/Target/X86/X86InstrInfo.cpp	Fri May 23 19:09:13 2003
@@ -6,7 +6,7 @@
 
 #include "X86InstrInfo.h"
 #include "X86.h"
-#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
 
 #define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES)
 #define IMPREGSLIST(NAME, ...) \
@@ -36,6 +36,34 @@
 
 X86InstrInfo::X86InstrInfo()
   : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+}
+
+
+// createNOPinstr - returns the target's implementation of NOP, which is
+// usually a pseudo-instruction, implemented by a degenerate version of
+// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
+//
+MachineInstr* X86InstrInfo::createNOPinstr() const {
+  return BuildMI(X86::XCHGrr16, 2).addReg(X86::AX).addReg(X86::AX);
+}
+
+
+// isNOPinstr - since we no longer have a special NOP opcode, we need to know
+// if a given instruction is interpreted as an `official' NOP instr, i.e.,
+// there may be more than one way to `do nothing' but only one canonical
+// way to slack off.
+//
+bool X86InstrInfo::isNOPinstr(const MachineInstr &MI) const {
+  // Make sure the instruction is EXACTLY `xchg ax, ax'
+  if (MI.getOpcode() == X86::XCHGrr16 && MI.getNumOperands() == 2) {
+    const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
+    if (op0.isMachineRegister() && op0.getMachineRegNum() == X86::AX &&
+        op1.isMachineRegister() && op1.getMachineRegNum() == X86::AX)
+    {
+      return true;
+    }
+  }
+  return false;
 }
 
 


Index: llvm/lib/Target/X86/X86InstrInfo.h
diff -u llvm/lib/Target/X86/X86InstrInfo.h:1.21 llvm/lib/Target/X86/X86InstrInfo.h:1.22
--- llvm/lib/Target/X86/X86InstrInfo.h:1.21	Tue Jan 14 15:59:16 2003
+++ llvm/lib/Target/X86/X86InstrInfo.h	Fri May 23 19:09:13 2003
@@ -148,6 +148,19 @@
   ///
   virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
 
+  /// createNOPinstr - returns the target's implementation of NOP, which is
+  /// usually a pseudo-instruction, implemented by a degenerate version of
+  /// another instruction, e.g. X86: `xchg ax, ax'; SparcV9: `sethi r0, r0, r0'
+  ///
+  MachineInstr* createNOPinstr() const;
+
+  /// isNOPinstr - since we no longer have a special NOP opcode, we need to know
+  /// if a given instruction is interpreted as an `official' NOP instr, i.e.,
+  /// there may be more than one way to `do nothing' but only one canonical
+  /// way to slack off.
+  ///
+  bool isNOPinstr(const MachineInstr &MI) const;
+
   /// print - Print out an x86 instruction in intel syntax
   ///
   virtual void print(const MachineInstr *MI, std::ostream &O,