[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrSelection.cpp SparcRegClassInfo.cpp SparcRegInfo.cpp
Misha Brukman
brukman at cs.uiuc.edu
Wed May 21 13:00:01 PDT 2003
Changes in directory llvm/lib/Target/Sparc:
SparcInstrSelection.cpp updated: 1.89 -> 1.90
SparcRegClassInfo.cpp updated: 1.18 -> 1.19
SparcRegInfo.cpp updated: 1.92 -> 1.93
---
Log message:
Namespacified `vector' and `cerr' to always use the `std::' namespace.
Eliminated `using' directives.
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.89 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.90
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.89 Tue May 20 15:32:23 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp Wed May 21 12:59:06 2003
@@ -24,10 +24,9 @@
#include "llvm/ConstantHandling.h"
#include "Support/MathExtras.h"
#include <math.h>
-using std::vector;
static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node,
- vector<MachineInstr*>& mvec) {
+ std::vector<MachineInstr*>& mvec) {
mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue())
.addReg(Node->rightChild()->getValue())
.addRegDef(Node->getValue()));
@@ -73,7 +72,7 @@
}
static Value*
-FoldGetElemChain(InstrTreeNode* ptrNode, vector<Value*>& chainIdxVec,
+FoldGetElemChain(InstrTreeNode* ptrNode, std::vector<Value*>& chainIdxVec,
bool lastInstHasLeadingNonZero)
{
InstructionNode* gepNode = dyn_cast<InstructionNode>(ptrNode);
@@ -164,7 +163,7 @@
static Value *
GetGEPInstArgs(InstructionNode* gepNode,
- vector<Value*>& idxVec,
+ std::vector<Value*>& idxVec,
bool& allConstantIndices)
{
allConstantIndices = true;
@@ -221,7 +220,7 @@
static Value*
GetMemInstArgs(InstructionNode* memInstrNode,
- vector<Value*>& idxVec,
+ std::vector<Value*>& idxVec,
bool& allConstantIndices)
{
allConstantIndices = false;
@@ -745,7 +744,7 @@
Value* optArgVal2, /* Use optArgVal2 if not NULL */
unsigned optShiftNum, /* else use optShiftNum */
Instruction* destVal,
- vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi)
{
assert((optArgVal2 != NULL || optShiftNum <= 64) &&
@@ -788,7 +787,7 @@
static inline unsigned
CreateMulConstInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
- vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi)
{
/* Use max. multiply cost, viz., cost of MULX */
@@ -869,7 +868,7 @@
Function* F,
Value* lval, Value* rval,
Instruction* destVal,
- vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi)
{
Value* constOp;
@@ -892,7 +891,7 @@
static inline void
CreateMulInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
- vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi,
MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
{
@@ -941,7 +940,7 @@
static inline void
CreateDivConstInstruction(TargetMachine &target,
const InstructionNode* instrNode,
- vector<MachineInstr*>& mvec)
+ std::vector<MachineInstr*>& mvec)
{
Value* LHS = instrNode->leftChild()->getValue();
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
@@ -1005,7 +1004,7 @@
Instruction* result,
unsigned tsize,
Value* numElementsVal,
- vector<MachineInstr*>& getMvec)
+ std::vector<MachineInstr*>& getMvec)
{
Value* totalSizeVal;
MachineInstr* M;
@@ -1076,7 +1075,7 @@
Instruction* result,
unsigned tsize,
unsigned numElements,
- vector<MachineInstr*>& getMvec)
+ std::vector<MachineInstr*>& getMvec)
{
assert(tsize > 0 && "Illegal (zero) type size for alloca");
assert(result && result->getParent() &&
@@ -1131,13 +1130,13 @@
static void
SetOperandsForMemInstr(unsigned Opcode,
- vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
InstructionNode* vmInstrNode,
const TargetMachine& target)
{
Instruction* memInst = vmInstrNode->getInstruction();
// Index vector, ptr value, and flag if all indices are const.
- vector<Value*> idxVec;
+ std::vector<Value*> idxVec;
bool allConstantIndices;
Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices);
@@ -1176,7 +1175,7 @@
Value* idxVal = idxVec[firstIdxIsZero];
- vector<MachineInstr*> mulVec;
+ std::vector<MachineInstr*> mulVec;
Instruction* addr = new TmpInstruction(Type::ULongTy, memInst);
MachineCodeForInstruction::get(memInst).addTemp(addr);
@@ -1366,7 +1365,7 @@
int ruleForNode,
short* nts,
TargetMachine &target,
- vector<MachineInstr*>& mvec)
+ std::vector<MachineInstr*>& mvec)
{
bool checkCast = false; // initialize here to use fall-through
bool maskUnsignedResult = false;
@@ -2171,7 +2170,7 @@
intArgReg = new TmpInstruction(Type::IntTy, argVal);
destMCFI.addTemp(intArgReg);
- vector<MachineInstr*> copyMvec;
+ std::vector<MachineInstr*> copyMvec;
target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
callInstr->getParent()->getParent(),
argVal, (TmpInstruction*) intArgReg,
@@ -2256,7 +2255,7 @@
ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
else
{
- vector<MachineInstr*> minstrVec;
+ std::vector<MachineInstr*> minstrVec;
Instruction* instr = subtreeRoot->getInstruction();
target.getInstrInfo().
CreateCopyInstructionsByType(target,
Index: llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.18 llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.19
--- llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.18 Wed Jan 15 13:50:44 2003
+++ llvm/lib/Target/Sparc/SparcRegClassInfo.cpp Wed May 21 12:59:06 2003
@@ -7,8 +7,6 @@
#include "SparcRegClassInfo.h"
#include "llvm/Type.h"
#include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME!
-using std::cerr;
-using std::vector;
//-----------------------------------------------------------------------------
// Int Register Class - method for coloring a node in the interference graph.
@@ -23,11 +21,13 @@
// If both above fail, spill.
//
//-----------------------------------------------------------------------------
-void SparcIntRegClass::colorIGNode(IGNode * Node, vector<bool> &IsColorUsedArr) const {
+void SparcIntRegClass::colorIGNode(IGNode * Node,
+ std::vector<bool> &IsColorUsedArr) const
+{
LiveRange *LR = Node->getParentLR();
if( DEBUG_RA ) {
- cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
+ std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
printSet(*LR);
}
@@ -43,18 +43,18 @@
// there are no call interferences. Otherwise, it will get spilled.
if (DEBUG_RA)
- cerr << "\n -Coloring with sug color: " << SugCol;
+ std::cerr << "\n -Coloring with sug color: " << SugCol;
LR->setColor( LR->getSuggestedColor() );
return;
}
else if(DEBUG_RA)
- cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
+ std::cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
}
- else if ( DEBUG_RA ) { // can't allocate the suggested col
- cerr << " \n Could NOT allocate the suggested color (already used) ";
- printSet(*LR); cerr << "\n";
+ else if (DEBUG_RA) { // can't allocate the suggested col
+ std::cerr << "\n Could NOT allocate the suggested color (already used) ";
+ printSet(*LR); std::cerr << "\n";
}
}
@@ -81,7 +81,7 @@
if( ColorFound) {
LR->setColor(c); // first color found in preffered order
- if (DEBUG_RA) cerr << "\n Colored after first search with col " << c ;
+ if (DEBUG_RA) std::cerr << "\n Colored after first search with col " << c;
}
// if color is not found because of call interference
@@ -103,7 +103,8 @@
// since LR span across calls, must save across calls
//
LR->markForSaveAcrossCalls();
- if(DEBUG_RA) cerr << "\n Colored after SECOND search with col " << c ;
+ if (DEBUG_RA)
+ std::cerr << "\n Colored after SECOND search with col " << c;
}
}
@@ -136,7 +137,8 @@
//
//----------------------------------------------------------------------------
void SparcFloatRegClass::colorIGNode(IGNode * Node,
- vector<bool> &IsColorUsedArr) const{
+ std::vector<bool> &IsColorUsedArr) const
+{
LiveRange *LR = Node->getParentLR();
// Mark the second color for double-precision registers:
@@ -172,8 +174,8 @@
LR->setColor( LR->getSuggestedColor() );
return;
} else if (DEBUG_RA) { // can't allocate the suggested col
- cerr << " Could NOT allocate the suggested color for LR ";
- printSet(*LR); cerr << "\n";
+ std::cerr << " Could NOT allocate the suggested color for LR ";
+ printSet(*LR); std::cerr << "\n";
}
}
@@ -247,9 +249,11 @@
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
-int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
- unsigned Start, unsigned End,
- vector<bool> &IsColorUsedArr) const {
+int SparcFloatRegClass::findFloatColor
+(const LiveRange *LR,
+ unsigned Start, unsigned End,
+ std::vector<bool> &IsColorUsedArr) const
+{
bool ColorFound = false;
unsigned c;
Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.92 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.93
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.92 Tue May 20 15:32:24 2003
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp Wed May 21 12:59:06 2003
@@ -19,8 +19,6 @@
#include "llvm/iOther.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
-using std::cerr;
-using std::vector;
enum {
BadRegClass = ~0
@@ -665,7 +663,7 @@
PhyRegAlloc &PRA, LiveRange* LR,
unsigned regType, unsigned RegClassID,
int UniArgRegOrNone, unsigned argNo,
- std::vector<MachineInstr *>& AddedInstrnsBefore)
+ std::vector<MachineInstr*> &AddedInstrnsBefore)
const
{
MachineInstr *AdMI;
@@ -778,7 +776,7 @@
LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
if (!RetValLR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
+ std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
assert(RetValLR && "ERR:No LR for non-void return value");
}
@@ -840,7 +838,7 @@
// Now color all args of the call instruction
//-------------------------------------------
- std::vector<MachineInstr *> AddedInstrnsBefore;
+ std::vector<MachineInstr*> AddedInstrnsBefore;
unsigned NumOfCallArgs = argDesc->getNumArgs();
@@ -882,7 +880,7 @@
// not possible to have a null LR since all args (even consts)
// must be defined before
if (!LR) {
- cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
+ std::cerr <<" ERROR: In call instr, no LR for arg: " <<RAV(CallArg)<<"\n";
assert(LR && "NO LR for call arg");
}
@@ -929,13 +927,13 @@
// If we added any instruction before the call instruction, verify
// that they are in the proper order and if not, reorder them
//
- std::vector<MachineInstr *> ReorderedVec;
+ std::vector<MachineInstr*> ReorderedVec;
if (!AddedInstrnsBefore.empty()) {
if (DEBUG_RA) {
- cerr << "\nCalling reorder with instrns: \n";
+ std::cerr << "\nCalling reorder with instrns: \n";
for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
- cerr << *(AddedInstrnsBefore[i]);
+ std::cerr << *(AddedInstrnsBefore[i]);
}
OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
@@ -943,9 +941,9 @@
&& "Dropped some instructions when reordering!");
if (DEBUG_RA) {
- cerr << "\nAfter reordering instrns: \n";
+ std::cerr << "\nAfter reordering instrns: \n";
for(unsigned i = 0; i < ReorderedVec.size(); i++)
- cerr << *ReorderedVec[i];
+ std::cerr << *ReorderedVec[i];
}
}
@@ -980,7 +978,7 @@
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
if (!LR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
+ std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
assert(0 && "No LR for return value of non-void method");
}
@@ -1015,7 +1013,7 @@
LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
if (!LR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
+ std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
// assert( LR && "No LR for return value of non-void method");
return;
}
@@ -1060,7 +1058,7 @@
else { // if the LR is spilled
cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
LR->getSpillOffFromFP(), UniRetReg, regType);
- //cerr << "\nCopied the return value from stack\n";
+ //std::cerr << "\nCopied the return value from stack\n";
}
} // if there is a return value
@@ -1094,7 +1092,7 @@
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::cpReg2RegMI(vector<MachineInstr*>& mvec,
+UltraSparcRegInfo::cpReg2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
@@ -1152,7 +1150,7 @@
void
-UltraSparcRegInfo::cpReg2MemMI(vector<MachineInstr*>& mvec,
+UltraSparcRegInfo::cpReg2MemMI(std::vector<MachineInstr*>& mvec,
unsigned SrcReg,
unsigned DestPtrReg,
int Offset, int RegType,
@@ -1206,7 +1204,7 @@
void
-UltraSparcRegInfo::cpMem2RegMI(vector<MachineInstr*>& mvec,
+UltraSparcRegInfo::cpMem2RegMI(std::vector<MachineInstr*>& mvec,
unsigned SrcPtrReg,
int Offset,
unsigned DestReg,
@@ -1264,7 +1262,7 @@
void
UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
- vector<MachineInstr*>& mvec) const {
+ std::vector<MachineInstr*>& mvec) const {
int RegType = getRegType(Src->getType());
MachineInstr * MI = NULL;
@@ -1306,11 +1304,12 @@
void
-UltraSparcRegInfo::insertCallerSavingCode(vector<MachineInstr*>& instrnsBefore,
- vector<MachineInstr*>& instrnsAfter,
- MachineInstr *CallMI,
- const BasicBlock *BB,
- PhyRegAlloc &PRA) const
+UltraSparcRegInfo::insertCallerSavingCode
+(std::vector<MachineInstr*> &instrnsBefore,
+ std::vector<MachineInstr*> &instrnsAfter,
+ MachineInstr *CallMI,
+ const BasicBlock *BB,
+ PhyRegAlloc &PRA) const
{
assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
@@ -1377,7 +1376,7 @@
int StackOff =
PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
- vector<MachineInstr*> AdIBef, AdIAft;
+ std::vector<MachineInstr*> AdIBef, AdIAft;
//---- Insert code for pushing the reg on stack ----------
@@ -1439,11 +1438,11 @@
PushedRegSet.insert(Reg);
if(DEBUG_RA) {
- cerr << "\nFor call inst:" << *CallMI;
- cerr << " -inserted caller saving instrs: Before:\n\t ";
+ std::cerr << "\nFor call inst:" << *CallMI;
+ std::cerr << " -inserted caller saving instrs: Before:\n\t ";
for_each(instrnsBefore.begin(), instrnsBefore.end(),
std::mem_fun(&MachineInstr::dump));
- cerr << " -and After:\n\t ";
+ std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
}
@@ -1465,25 +1464,25 @@
void UltraSparcRegInfo::printReg(const LiveRange *LR) {
unsigned RegClassID = LR->getRegClassID();
- cerr << " *Node " << (LR->getUserIGNode())->getIndex();
+ std::cerr << " *Node " << (LR->getUserIGNode())->getIndex();
if (!LR->hasColor()) {
- cerr << " - could not find a color\n";
+ std::cerr << " - could not find a color\n";
return;
}
// if a color is found
- cerr << " colored with color "<< LR->getColor();
+ std::cerr << " colored with color "<< LR->getColor();
if (RegClassID == IntRegClassID) {
- cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
+ std::cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
} else if (RegClassID == FloatRegClassID) {
- cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
+ std::cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
if( LR->getType() == Type::DoubleTy)
- cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
- cerr << "]\n";
+ std::cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
+ std::cerr << "]\n";
}
}
@@ -1545,7 +1544,7 @@
do {
CouldMoveAll = true;
- std::vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
+ std::vector<MachineInstr*>::iterator DefIt = UnordVec.begin();
for( ; DefIt != UnordVec.end(); ++DefIt ) {
@@ -1555,7 +1554,7 @@
if( DefInst == NULL) continue;
- //cerr << "\nInst in UnordVec = " << *DefInst;
+ //std::cerr << "\nInst in UnordVec = " << *DefInst;
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
@@ -1566,7 +1565,7 @@
// If the operand in DefInst is a def ...
bool DefEqUse = false;
- std::vector<MachineInstr *>::iterator UseIt = DefIt;
+ std::vector<MachineInstr*>::iterator UseIt = DefIt;
UseIt++;
for( ; UseIt != UnordVec.end(); ++UseIt ) {
@@ -1587,7 +1586,7 @@
// if Def and this use are the same, it means that this use
// is destroyed by a def before it is used
- // cerr << "\nCouldn't move " << *DefInst;
+ // std::cerr << "\nCouldn't move " << *DefInst;
DefEqUse = true;
CouldMoveAll = false;
@@ -1604,7 +1603,7 @@
// after examining all the instructions that follow the DefInst
// if there are no dependencies, we can move it to the OrdVec
- // cerr << "Moved to Ord: " << *DefInst;
+ // std::cerr << "Moved to Ord: " << *DefInst;
moveInst2OrdVec(OrdVec, DefInst, PRA);
@@ -1623,9 +1622,9 @@
} while(!CouldMoveAll);
if (DebugPrint && DEBUG_RA) {
- cerr << "\nAdded instructions were reordered to:\n";
+ std::cerr << "\nAdded instructions were reordered to:\n";
for(unsigned i=0; i < OrdVec.size(); i++)
- cerr << *OrdVec[i];
+ std::cerr << *OrdVec[i];
}
}
@@ -1633,7 +1632,7 @@
-void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
+void UltraSparcRegInfo::moveInst2OrdVec(std::vector<MachineInstr*> &OrdVec,
MachineInstr *UnordInst,
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
@@ -1645,7 +1644,7 @@
// before in the OrdVec
bool DefEqUse = false;
- std::vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
+ std::vector<MachineInstr*>::iterator OrdIt = OrdVec.begin();
for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
@@ -1657,7 +1656,7 @@
if( DefOp.opIsDef() &&
DefOp.getType() == MachineOperand::MO_MachineRegister) {
- //cerr << "\nDefining Ord Inst: " << *OrdInst;
+ //std::cerr << "\nDefining Ord Inst: " << *OrdInst;
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
@@ -1678,9 +1677,9 @@
PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
// Save the UReg (%ox) on stack before it's destroyed
- vector<MachineInstr*> mvec;
+ std::vector<MachineInstr*> mvec;
cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
- for (vector<MachineInstr*>::iterator MI=mvec.begin();
+ for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
MI != mvec.end(); ++MI)
OrdIt = 1+OrdVec.insert(OrdIt, *MI);
@@ -1693,14 +1692,14 @@
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
if( DEBUG_RA ) {
- cerr << "\nFixed CIRCULAR references by reordering:";
- cerr << "\nBefore CIRCULAR Reordering:\n";
- cerr << *UnordInst;
- cerr << *OrdInst;
+ std::cerr << "\nFixed CIRCULAR references by reordering:";
+ std::cerr << "\nBefore CIRCULAR Reordering:\n";
+ std::cerr << *UnordInst;
+ std::cerr << *OrdInst;
- cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
+ std::cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
for(unsigned i=0; i < OrdVec.size(); i++)
- cerr << *(OrdVec[i]);
+ std::cerr << *(OrdVec[i]);
}
// Do not copy the UseInst to OrdVec
@@ -1717,7 +1716,7 @@
// We didn't find a def in the OrdVec, so just append this inst
OrdVec.push_back( UnordInst );
- //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
+ //std::cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
}
}// if the operand in UnordInst is a use
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