"
Memory Safety Without Runtime Checks or Garbage
Collection"
Dinakar Dhurjati, Sumant Kowshik, Vikram Adve and
From lattner at cs.uiuc.edu Wed May 21 11:18:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 11:18:00 2003
Subject: [llvm-commits] CVS: llvm/www/pubs/2002-08-08-CASES02-ControlC.html
Message-ID: <200305211617.LAA02561@tank.cs.uiuc.edu>
Changes in directory llvm/www/pubs:
2002-08-08-CASES02-ControlC.html updated: 1.2 -> 1.3
---
Log message:
Add link to presentation
---
Diffs of the changes:
Index: llvm/www/pubs/2002-08-08-CASES02-ControlC.html
diff -u llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.2 llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.3
--- llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.2 Wed May 21 11:14:01 2003
+++ llvm/www/pubs/2002-08-08-CASES02-ControlC.html Wed May 21 11:17:07 2003
@@ -51,6 +51,7 @@
Bibtex Entry:
From lattner at cs.uiuc.edu Wed May 21 11:19:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 11:19:00 2003
Subject: [llvm-commits] CVS: llvm/www/pubs/2002-08-08-CASES02-ControlC.html
Message-ID: <200305211618.LAA02604@tank.cs.uiuc.edu>
Changes in directory llvm/www/pubs:
2002-08-08-CASES02-ControlC.html updated: 1.3 -> 1.4
---
Log message:
Fix horrible copy/pasto
---
Diffs of the changes:
Index: llvm/www/pubs/2002-08-08-CASES02-ControlC.html
diff -u llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.3 llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.4
--- llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.3 Wed May 21 11:17:07 2003
+++ llvm/www/pubs/2002-08-08-CASES02-ControlC.html Wed May 21 11:18:03 2003
@@ -51,7 +51,7 @@
Bibtex Entry:
From lattner at cs.uiuc.edu Wed May 21 11:24:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 11:24:00 2003
Subject: [llvm-commits] CVS: llvm/www/www-index.html
Message-ID: <200305211623.LAA02667@tank.cs.uiuc.edu>
Changes in directory llvm/www:
www-index.html updated: 1.36 -> 1.37
---
Log message:
Add new news item
Kill date suffixes in new section
---
Diffs of the changes:
Index: llvm/www/www-index.html
diff -u llvm/www/www-index.html:1.36 llvm/www/www-index.html:1.37
--- llvm/www/www-index.html:1.36 Wed May 21 11:14:59 2003
+++ llvm/www/www-index.html Wed May 21 11:23:28 2003
@@ -235,33 +235,39 @@
- | May 8th, 2003 |
+ May 21, 2003 |
+ - |
+ Added some new documents to the
+ publications section. |
+
+
+ | May 8, 2003 |
- |
Switched over to the rewritten C front-end which supports variable argument functions and has no known miscompilation bugs. |
- | Mar 4th, 2003 |
+ Mar 4, 2003 |
- |
Added a new
Alias Analysis
document, describing Alias Analysis in LLVM. |
- | Feb 6th, 2003 |
+ Feb 6, 2003 |
- |
Added a new
open projects
page, listing some desired improvements to LLVM. |
- | Jan 22nd, 2003 |
+ Jan 22, 2003 |
- |
Implemented a new
automated nightly testing
framework. |
- | Dec 14th, 2002 |
+ Dec 14, 2002 |
- |
Added Chris Lattner's to the publications list. |
- | Oct 28th, 2002 |
+ Oct 28, 2002 |
- |
A new
|
- | Sep 5th, 2002 |
+ Sep 5, 2002 |
- |
An initial draft of the
|
- | Sep 3rd, 2002 |
+ Sep 3, 2002 |
- |
A new
|
- | Aug 8th, 2002 |
+ Aug 8, 2002 |
- |
Published the Writing
An LLVM Pass document. |
- | Jul 24th, 2002 |
+ Jul 24, 2002 |
- |
Published the LLVM
Getting Started Guide. |
- | Jul 1st, 2002 |
+ Jul 1, 2002 |
- |
Finished providing
initial information about LLVM, we now
consider the site to have "gone public". |
- | Jun 28th, 2002 |
+ Jun 28, 2002 |
- |
Added The
@@ -326,7 +332,7 @@
Strategy document. |
- | Jun 13th, 2002 |
+ Jun 13, 2002 |
- |
Web page first published. |
From kowshik at cs.uiuc.edu Wed May 21 12:16:01 2003
From: kowshik at cs.uiuc.edu (Sumant Kowshik)
Date: Wed May 21 12:16:01 2003
Subject: [llvm-commits] CVS: llvm/www/pubs/2002-08-08-CASES02-ControlC.html
Message-ID: <200305211715.MAA03642@tank.cs.uiuc.edu>
Changes in directory llvm/www/pubs:
2002-08-08-CASES02-ControlC.html updated: 1.4 -> 1.5
---
Log message:
---
Diffs of the changes:
Index: llvm/www/pubs/2002-08-08-CASES02-ControlC.html
diff -u llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.4 llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.5
--- llvm/www/pubs/2002-08-08-CASES02-ControlC.html:1.4 Wed May 21 11:18:03 2003
+++ llvm/www/pubs/2002-08-08-CASES02-ControlC.html Wed May 21 12:09:18 2003
@@ -6,7 +6,7 @@
-
Ensuring Code Safety Without Runtime Checks for Real-Time Control Systems
Sumant Kowshik, Dinakar Dhurjati and
Vikram Adve
From kowshik at cs.uiuc.edu Wed May 21 12:17:00 2003
From: kowshik at cs.uiuc.edu (Sumant Kowshik)
Date: Wed May 21 12:17:00 2003
Subject: [llvm-commits] CVS: llvm/www/pubs/2003-05-05-LCTES03-CodeSafety.html
Message-ID: <200305211716.MAA03670@tank.cs.uiuc.edu>
Changes in directory llvm/www/pubs:
2003-05-05-LCTES03-CodeSafety.html updated: 1.1 -> 1.2
---
Log message:
---
Diffs of the changes:
Index: llvm/www/pubs/2003-05-05-LCTES03-CodeSafety.html
diff -u llvm/www/pubs/2003-05-05-LCTES03-CodeSafety.html:1.1 llvm/www/pubs/2003-05-05-LCTES03-CodeSafety.html:1.2
--- llvm/www/pubs/2003-05-05-LCTES03-CodeSafety.html:1.1 Wed May 21 10:02:57 2003
+++ llvm/www/pubs/2003-05-05-LCTES03-CodeSafety.html Wed May 21 12:15:41 2003
@@ -6,7 +6,7 @@
-
Memory Safety Without Runtime Checks or Garbage Collection
Dinakar Dhurjati, Sumant Kowshik,
Vikram Adve and
From lattner at cs.uiuc.edu Wed May 21 12:58:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 12:58:02 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Assembler/2003-05-21-ConstantShiftExpr.ll
Message-ID: <200305211734.MAA28267@apoc.cs.uiuc.edu>
Changes in directory llvm/test/Regression/Assembler:
2003-05-21-ConstantShiftExpr.ll added (r1.1)
---
Log message:
New testcase
---
Diffs of the changes:
Index: llvm/test/Regression/Assembler/2003-05-21-ConstantShiftExpr.ll
diff -c /dev/null llvm/test/Regression/Assembler/2003-05-21-ConstantShiftExpr.ll:1.1
*** /dev/null Wed May 21 12:34:34 2003
--- llvm/test/Regression/Assembler/2003-05-21-ConstantShiftExpr.ll Wed May 21 12:34:24 2003
***************
*** 0 ****
--- 1,3 ----
+ ; Test that shift instructions can be used in constant expressions.
+
+ global int shl (int 7, ubyte 19)
From lattner at cs.uiuc.edu Wed May 21 12:59:02 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 12:59:02 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Assembler/2003-05-21-MalformedShiftCrash.llx
Message-ID: <200305211746.MAA29498@apoc.cs.uiuc.edu>
Changes in directory llvm/test/Regression/Assembler:
2003-05-21-MalformedShiftCrash.llx added (r1.1)
---
Log message:
New testcase, found by inspection
---
Diffs of the changes:
Index: llvm/test/Regression/Assembler/2003-05-21-MalformedShiftCrash.llx
diff -c /dev/null llvm/test/Regression/Assembler/2003-05-21-MalformedShiftCrash.llx:1.1
*** /dev/null Wed May 21 12:46:16 2003
--- llvm/test/Regression/Assembler/2003-05-21-MalformedShiftCrash.llx Wed May 21 12:46:02 2003
***************
*** 0 ****
--- 1,4 ----
+ ; Found by inspection of the code
+ ; RUN: as < %s 2>&1 | grep "Shift constant expression"
+
+ global int shr (float 1.0, ubyte 2)
From lattner at cs.uiuc.edu Wed May 21 12:59:04 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 12:59:04 2003
Subject: [llvm-commits] CVS: llvm/lib/AsmParser/llvmAsmParser.y
Message-ID: <200305211749.MAA29597@apoc.cs.uiuc.edu>
Changes in directory llvm/lib/AsmParser:
llvmAsmParser.y updated: 1.112 -> 1.113
---
Log message:
Fix bugs:
Assembler/2003-05-21-MalformedShiftCrash.llx
Assembler/2003-05-21-ConstantShiftExpr.ll
---
Diffs of the changes:
Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.112 llvm/lib/AsmParser/llvmAsmParser.y:1.113
--- llvm/lib/AsmParser/llvmAsmParser.y:1.112 Wed May 21 11:06:56 2003
+++ llvm/lib/AsmParser/llvmAsmParser.y Wed May 21 12:48:56 2003
@@ -1094,7 +1094,9 @@
| ShiftOps '(' ConstVal ',' ConstVal ')' {
if ($5->getType() != Type::UByteTy)
ThrowException("Shift count for shift constant must be unsigned byte!");
- $$ = ConstantExpr::get($1, $3, $5);
+ if (!$3->getType()->isIntegral())
+ ThrowException("Shift constant expression requires integral operand!");
+ $$ = ConstantExpr::getShift($1, $3, $5);
};
From lattner at cs.uiuc.edu Wed May 21 12:59:06 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 12:59:06 2003
Subject: [llvm-commits] CVS: llvm/include/llvm/Constants.h
Message-ID: <200305211749.MAA29608@apoc.cs.uiuc.edu>
Changes in directory llvm/include/llvm:
Constants.h updated: 1.22 -> 1.23
---
Log message:
New method
---
Diffs of the changes:
Index: llvm/include/llvm/Constants.h
diff -u llvm/include/llvm/Constants.h:1.22 llvm/include/llvm/Constants.h:1.23
--- llvm/include/llvm/Constants.h:1.22 Wed May 14 12:49:52 2003
+++ llvm/include/llvm/Constants.h Wed May 21 12:49:08 2003
@@ -486,6 +486,9 @@
/// Binary constant expr - Use with binary operators...
static Constant *get(unsigned Opcode, Constant *C1, Constant *C2);
+ /// getShift - Return a shift left or shift right constant expr
+ static Constant *getShift(unsigned Opcode, Constant *C1, Constant *C2);
+
/// Getelementptr form...
static Constant *getGetElementPtr(Constant *C,
const std::vector &IdxList);
From lattner at cs.uiuc.edu Wed May 21 12:59:08 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 12:59:08 2003
Subject: [llvm-commits] CVS: llvm/lib/VMCore/Constants.cpp
Message-ID: <200305211749.MAA29619@apoc.cs.uiuc.edu>
Changes in directory llvm/lib/VMCore:
Constants.cpp updated: 1.39 -> 1.40
---
Log message:
Add support for shift constant expressions
---
Diffs of the changes:
Index: llvm/lib/VMCore/Constants.cpp
diff -u llvm/lib/VMCore/Constants.cpp:1.39 llvm/lib/VMCore/Constants.cpp:1.40
--- llvm/lib/VMCore/Constants.cpp:1.39 Thu May 15 14:37:20 2003
+++ llvm/lib/VMCore/Constants.cpp Wed May 21 12:49:25 2003
@@ -649,6 +649,12 @@
}
Constant *ConstantExpr::get(unsigned Opcode, Constant *C1, Constant *C2) {
+ // Check the operands for consistency first
+ assert((Opcode >= Instruction::BinaryOpsBegin &&
+ Opcode < Instruction::BinaryOpsEnd) &&
+ "Invalid opcode in binary constant expression");
+ assert(C1->getType() == C2->getType() &&
+ "Operand types in binary constant expression should match");
if (Constant *FC = ConstantFoldBinaryInstruction(Opcode, C1, C2))
return FC; // Fold a few common cases...
@@ -659,19 +665,36 @@
ConstantExpr *Result = ExprConstants.get(C1->getType(), Key);
if (Result) return Result;
- // Its not in the table so create a new one and put it in the table.
+ // It's not in the table so create a new one and put it in the table.
+ Result = new ConstantExpr(Opcode, C1, C2);
+ ExprConstants.add(C1->getType(), Key, Result);
+ return Result;
+}
+
+/// getShift - Return a shift left or shift right constant expr
+Constant *ConstantExpr::getShift(unsigned Opcode, Constant *C1, Constant *C2) {
// Check the operands for consistency first
- assert((Opcode >= Instruction::BinaryOpsBegin &&
- Opcode < Instruction::BinaryOpsEnd) &&
+ assert((Opcode == Instruction::Shl ||
+ Opcode == Instruction::Shr) &&
"Invalid opcode in binary constant expression");
+ assert(C1->getType()->isIntegral() && C2->getType() == Type::UByteTy &&
+ "Invalid operand types for Shift constant expr!");
- assert(C1->getType() == C2->getType() &&
- "Operand types in binary constant expression should match");
+ if (Constant *FC = ConstantFoldShiftInstruction(Opcode, C1, C2))
+ return FC; // Fold a few common cases...
+
+ // Look up the constant in the table first to ensure uniqueness
+ std::vector argVec(1, C1); argVec.push_back(C2);
+ const ExprMapKeyType &Key = std::make_pair(Opcode, argVec);
+ ConstantExpr *Result = ExprConstants.get(C1->getType(), Key);
+ if (Result) return Result;
+ // It's not in the table so create a new one and put it in the table.
Result = new ConstantExpr(Opcode, C1, C2);
ExprConstants.add(C1->getType(), Key, Result);
return Result;
}
+
Constant *ConstantExpr::getGetElementPtr(Constant *C,
const std::vector &IdxList){
From brukman at cs.uiuc.edu Wed May 21 13:00:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed May 21 13:00:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrSelection.cpp SparcRegClassInfo.cpp SparcRegInfo.cpp
Message-ID: <200305211759.MAA15957@zion.cs.uiuc.edu>
Changes in directory llvm/lib/Target/Sparc:
SparcInstrSelection.cpp updated: 1.89 -> 1.90
SparcRegClassInfo.cpp updated: 1.18 -> 1.19
SparcRegInfo.cpp updated: 1.92 -> 1.93
---
Log message:
Namespacified `vector' and `cerr' to always use the `std::' namespace.
Eliminated `using' directives.
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.89 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.90
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.89 Tue May 20 15:32:23 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp Wed May 21 12:59:06 2003
@@ -24,10 +24,9 @@
#include "llvm/ConstantHandling.h"
#include "Support/MathExtras.h"
#include
-using std::vector;
static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node,
- vector& mvec) {
+ std::vector& mvec) {
mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue())
.addReg(Node->rightChild()->getValue())
.addRegDef(Node->getValue()));
@@ -73,7 +72,7 @@
}
static Value*
-FoldGetElemChain(InstrTreeNode* ptrNode, vector& chainIdxVec,
+FoldGetElemChain(InstrTreeNode* ptrNode, std::vector& chainIdxVec,
bool lastInstHasLeadingNonZero)
{
InstructionNode* gepNode = dyn_cast(ptrNode);
@@ -164,7 +163,7 @@
static Value *
GetGEPInstArgs(InstructionNode* gepNode,
- vector& idxVec,
+ std::vector& idxVec,
bool& allConstantIndices)
{
allConstantIndices = true;
@@ -221,7 +220,7 @@
static Value*
GetMemInstArgs(InstructionNode* memInstrNode,
- vector& idxVec,
+ std::vector& idxVec,
bool& allConstantIndices)
{
allConstantIndices = false;
@@ -745,7 +744,7 @@
Value* optArgVal2, /* Use optArgVal2 if not NULL */
unsigned optShiftNum, /* else use optShiftNum */
Instruction* destVal,
- vector& mvec,
+ std::vector& mvec,
MachineCodeForInstruction& mcfi)
{
assert((optArgVal2 != NULL || optShiftNum <= 64) &&
@@ -788,7 +787,7 @@
static inline unsigned
CreateMulConstInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
- vector& mvec,
+ std::vector& mvec,
MachineCodeForInstruction& mcfi)
{
/* Use max. multiply cost, viz., cost of MULX */
@@ -869,7 +868,7 @@
Function* F,
Value* lval, Value* rval,
Instruction* destVal,
- vector& mvec,
+ std::vector& mvec,
MachineCodeForInstruction& mcfi)
{
Value* constOp;
@@ -892,7 +891,7 @@
static inline void
CreateMulInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
- vector& mvec,
+ std::vector& mvec,
MachineCodeForInstruction& mcfi,
MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
{
@@ -941,7 +940,7 @@
static inline void
CreateDivConstInstruction(TargetMachine &target,
const InstructionNode* instrNode,
- vector& mvec)
+ std::vector& mvec)
{
Value* LHS = instrNode->leftChild()->getValue();
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
@@ -1005,7 +1004,7 @@
Instruction* result,
unsigned tsize,
Value* numElementsVal,
- vector& getMvec)
+ std::vector& getMvec)
{
Value* totalSizeVal;
MachineInstr* M;
@@ -1076,7 +1075,7 @@
Instruction* result,
unsigned tsize,
unsigned numElements,
- vector& getMvec)
+ std::vector& getMvec)
{
assert(tsize > 0 && "Illegal (zero) type size for alloca");
assert(result && result->getParent() &&
@@ -1131,13 +1130,13 @@
static void
SetOperandsForMemInstr(unsigned Opcode,
- vector& mvec,
+ std::vector& mvec,
InstructionNode* vmInstrNode,
const TargetMachine& target)
{
Instruction* memInst = vmInstrNode->getInstruction();
// Index vector, ptr value, and flag if all indices are const.
- vector idxVec;
+ std::vector idxVec;
bool allConstantIndices;
Value* ptrVal = GetMemInstArgs(vmInstrNode, idxVec, allConstantIndices);
@@ -1176,7 +1175,7 @@
Value* idxVal = idxVec[firstIdxIsZero];
- vector mulVec;
+ std::vector mulVec;
Instruction* addr = new TmpInstruction(Type::ULongTy, memInst);
MachineCodeForInstruction::get(memInst).addTemp(addr);
@@ -1366,7 +1365,7 @@
int ruleForNode,
short* nts,
TargetMachine &target,
- vector& mvec)
+ std::vector& mvec)
{
bool checkCast = false; // initialize here to use fall-through
bool maskUnsignedResult = false;
@@ -2171,7 +2170,7 @@
intArgReg = new TmpInstruction(Type::IntTy, argVal);
destMCFI.addTemp(intArgReg);
- vector copyMvec;
+ std::vector copyMvec;
target.getInstrInfo().CreateCodeToCopyFloatToInt(target,
callInstr->getParent()->getParent(),
argVal, (TmpInstruction*) intArgReg,
@@ -2256,7 +2255,7 @@
ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
else
{
- vector minstrVec;
+ std::vector minstrVec;
Instruction* instr = subtreeRoot->getInstruction();
target.getInstrInfo().
CreateCopyInstructionsByType(target,
Index: llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.18 llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.19
--- llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.18 Wed Jan 15 13:50:44 2003
+++ llvm/lib/Target/Sparc/SparcRegClassInfo.cpp Wed May 21 12:59:06 2003
@@ -7,8 +7,6 @@
#include "SparcRegClassInfo.h"
#include "llvm/Type.h"
#include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME!
-using std::cerr;
-using std::vector;
//-----------------------------------------------------------------------------
// Int Register Class - method for coloring a node in the interference graph.
@@ -23,11 +21,13 @@
// If both above fail, spill.
//
//-----------------------------------------------------------------------------
-void SparcIntRegClass::colorIGNode(IGNode * Node, vector &IsColorUsedArr) const {
+void SparcIntRegClass::colorIGNode(IGNode * Node,
+ std::vector &IsColorUsedArr) const
+{
LiveRange *LR = Node->getParentLR();
if( DEBUG_RA ) {
- cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
+ std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
printSet(*LR);
}
@@ -43,18 +43,18 @@
// there are no call interferences. Otherwise, it will get spilled.
if (DEBUG_RA)
- cerr << "\n -Coloring with sug color: " << SugCol;
+ std::cerr << "\n -Coloring with sug color: " << SugCol;
LR->setColor( LR->getSuggestedColor() );
return;
}
else if(DEBUG_RA)
- cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
+ std::cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
}
- else if ( DEBUG_RA ) { // can't allocate the suggested col
- cerr << " \n Could NOT allocate the suggested color (already used) ";
- printSet(*LR); cerr << "\n";
+ else if (DEBUG_RA) { // can't allocate the suggested col
+ std::cerr << "\n Could NOT allocate the suggested color (already used) ";
+ printSet(*LR); std::cerr << "\n";
}
}
@@ -81,7 +81,7 @@
if( ColorFound) {
LR->setColor(c); // first color found in preffered order
- if (DEBUG_RA) cerr << "\n Colored after first search with col " << c ;
+ if (DEBUG_RA) std::cerr << "\n Colored after first search with col " << c;
}
// if color is not found because of call interference
@@ -103,7 +103,8 @@
// since LR span across calls, must save across calls
//
LR->markForSaveAcrossCalls();
- if(DEBUG_RA) cerr << "\n Colored after SECOND search with col " << c ;
+ if (DEBUG_RA)
+ std::cerr << "\n Colored after SECOND search with col " << c;
}
}
@@ -136,7 +137,8 @@
//
//----------------------------------------------------------------------------
void SparcFloatRegClass::colorIGNode(IGNode * Node,
- vector &IsColorUsedArr) const{
+ std::vector &IsColorUsedArr) const
+{
LiveRange *LR = Node->getParentLR();
// Mark the second color for double-precision registers:
@@ -172,8 +174,8 @@
LR->setColor( LR->getSuggestedColor() );
return;
} else if (DEBUG_RA) { // can't allocate the suggested col
- cerr << " Could NOT allocate the suggested color for LR ";
- printSet(*LR); cerr << "\n";
+ std::cerr << " Could NOT allocate the suggested color for LR ";
+ printSet(*LR); std::cerr << "\n";
}
}
@@ -247,9 +249,11 @@
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
-int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
- unsigned Start, unsigned End,
- vector &IsColorUsedArr) const {
+int SparcFloatRegClass::findFloatColor
+(const LiveRange *LR,
+ unsigned Start, unsigned End,
+ std::vector &IsColorUsedArr) const
+{
bool ColorFound = false;
unsigned c;
Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.92 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.93
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.92 Tue May 20 15:32:24 2003
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp Wed May 21 12:59:06 2003
@@ -19,8 +19,6 @@
#include "llvm/iOther.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
-using std::cerr;
-using std::vector;
enum {
BadRegClass = ~0
@@ -665,7 +663,7 @@
PhyRegAlloc &PRA, LiveRange* LR,
unsigned regType, unsigned RegClassID,
int UniArgRegOrNone, unsigned argNo,
- std::vector& AddedInstrnsBefore)
+ std::vector &AddedInstrnsBefore)
const
{
MachineInstr *AdMI;
@@ -778,7 +776,7 @@
LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
if (!RetValLR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
+ std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
assert(RetValLR && "ERR:No LR for non-void return value");
}
@@ -840,7 +838,7 @@
// Now color all args of the call instruction
//-------------------------------------------
- std::vector AddedInstrnsBefore;
+ std::vector AddedInstrnsBefore;
unsigned NumOfCallArgs = argDesc->getNumArgs();
@@ -882,7 +880,7 @@
// not possible to have a null LR since all args (even consts)
// must be defined before
if (!LR) {
- cerr << " ERROR: In call instr, no LR for arg: " << RAV(CallArg) <<"\n";
+ std::cerr <<" ERROR: In call instr, no LR for arg: " < ReorderedVec;
+ std::vector ReorderedVec;
if (!AddedInstrnsBefore.empty()) {
if (DEBUG_RA) {
- cerr << "\nCalling reorder with instrns: \n";
+ std::cerr << "\nCalling reorder with instrns: \n";
for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
- cerr << *(AddedInstrnsBefore[i]);
+ std::cerr << *(AddedInstrnsBefore[i]);
}
OrderAddedInstrns(AddedInstrnsBefore, ReorderedVec, PRA);
@@ -943,9 +941,9 @@
&& "Dropped some instructions when reordering!");
if (DEBUG_RA) {
- cerr << "\nAfter reordering instrns: \n";
+ std::cerr << "\nAfter reordering instrns: \n";
for(unsigned i = 0; i < ReorderedVec.size(); i++)
- cerr << *ReorderedVec[i];
+ std::cerr << *ReorderedVec[i];
}
}
@@ -980,7 +978,7 @@
LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
if (!LR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
+ std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
assert(0 && "No LR for return value of non-void method");
}
@@ -1015,7 +1013,7 @@
LiveRange *LR = LRI.getLiveRangeForValue(RetVal);
if (!LR) {
- cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
+ std::cerr << "\nNo LR for:" << RAV(RetVal) << "\n";
// assert( LR && "No LR for return value of non-void method");
return;
}
@@ -1060,7 +1058,7 @@
else { // if the LR is spilled
cpMem2RegMI(RetAI->InstrnsBefore, getFramePointer(),
LR->getSpillOffFromFP(), UniRetReg, regType);
- //cerr << "\nCopied the return value from stack\n";
+ //std::cerr << "\nCopied the return value from stack\n";
}
} // if there is a return value
@@ -1094,7 +1092,7 @@
//---------------------------------------------------------------------------
void
-UltraSparcRegInfo::cpReg2RegMI(vector& mvec,
+UltraSparcRegInfo::cpReg2RegMI(std::vector& mvec,
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
@@ -1152,7 +1150,7 @@
void
-UltraSparcRegInfo::cpReg2MemMI(vector& mvec,
+UltraSparcRegInfo::cpReg2MemMI(std::vector& mvec,
unsigned SrcReg,
unsigned DestPtrReg,
int Offset, int RegType,
@@ -1206,7 +1204,7 @@
void
-UltraSparcRegInfo::cpMem2RegMI(vector& mvec,
+UltraSparcRegInfo::cpMem2RegMI(std::vector& mvec,
unsigned SrcPtrReg,
int Offset,
unsigned DestReg,
@@ -1264,7 +1262,7 @@
void
UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest,
- vector& mvec) const {
+ std::vector& mvec) const {
int RegType = getRegType(Src->getType());
MachineInstr * MI = NULL;
@@ -1306,11 +1304,12 @@
void
-UltraSparcRegInfo::insertCallerSavingCode(vector& instrnsBefore,
- vector& instrnsAfter,
- MachineInstr *CallMI,
- const BasicBlock *BB,
- PhyRegAlloc &PRA) const
+UltraSparcRegInfo::insertCallerSavingCode
+(std::vector &instrnsBefore,
+ std::vector &instrnsAfter,
+ MachineInstr *CallMI,
+ const BasicBlock *BB,
+ PhyRegAlloc &PRA) const
{
assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
@@ -1377,7 +1376,7 @@
int StackOff =
PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
- vector AdIBef, AdIAft;
+ std::vector AdIBef, AdIAft;
//---- Insert code for pushing the reg on stack ----------
@@ -1439,11 +1438,11 @@
PushedRegSet.insert(Reg);
if(DEBUG_RA) {
- cerr << "\nFor call inst:" << *CallMI;
- cerr << " -inserted caller saving instrs: Before:\n\t ";
+ std::cerr << "\nFor call inst:" << *CallMI;
+ std::cerr << " -inserted caller saving instrs: Before:\n\t ";
for_each(instrnsBefore.begin(), instrnsBefore.end(),
std::mem_fun(&MachineInstr::dump));
- cerr << " -and After:\n\t ";
+ std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
}
@@ -1465,25 +1464,25 @@
void UltraSparcRegInfo::printReg(const LiveRange *LR) {
unsigned RegClassID = LR->getRegClassID();
- cerr << " *Node " << (LR->getUserIGNode())->getIndex();
+ std::cerr << " *Node " << (LR->getUserIGNode())->getIndex();
if (!LR->hasColor()) {
- cerr << " - could not find a color\n";
+ std::cerr << " - could not find a color\n";
return;
}
// if a color is found
- cerr << " colored with color "<< LR->getColor();
+ std::cerr << " colored with color "<< LR->getColor();
if (RegClassID == IntRegClassID) {
- cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
+ std::cerr<< " [" << SparcIntRegClass::getRegName(LR->getColor()) << "]\n";
} else if (RegClassID == FloatRegClassID) {
- cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
+ std::cerr << "[" << SparcFloatRegClass::getRegName(LR->getColor());
if( LR->getType() == Type::DoubleTy)
- cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
- cerr << "]\n";
+ std::cerr << "+" << SparcFloatRegClass::getRegName(LR->getColor()+1);
+ std::cerr << "]\n";
}
}
@@ -1545,7 +1544,7 @@
do {
CouldMoveAll = true;
- std::vector::iterator DefIt = UnordVec.begin();
+ std::vector::iterator DefIt = UnordVec.begin();
for( ; DefIt != UnordVec.end(); ++DefIt ) {
@@ -1555,7 +1554,7 @@
if( DefInst == NULL) continue;
- //cerr << "\nInst in UnordVec = " << *DefInst;
+ //std::cerr << "\nInst in UnordVec = " << *DefInst;
// last operand is the def (unless for a store which has no def reg)
MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
@@ -1566,7 +1565,7 @@
// If the operand in DefInst is a def ...
bool DefEqUse = false;
- std::vector::iterator UseIt = DefIt;
+ std::vector::iterator UseIt = DefIt;
UseIt++;
for( ; UseIt != UnordVec.end(); ++UseIt ) {
@@ -1587,7 +1586,7 @@
// if Def and this use are the same, it means that this use
// is destroyed by a def before it is used
- // cerr << "\nCouldn't move " << *DefInst;
+ // std::cerr << "\nCouldn't move " << *DefInst;
DefEqUse = true;
CouldMoveAll = false;
@@ -1604,7 +1603,7 @@
// after examining all the instructions that follow the DefInst
// if there are no dependencies, we can move it to the OrdVec
- // cerr << "Moved to Ord: " << *DefInst;
+ // std::cerr << "Moved to Ord: " << *DefInst;
moveInst2OrdVec(OrdVec, DefInst, PRA);
@@ -1623,9 +1622,9 @@
} while(!CouldMoveAll);
if (DebugPrint && DEBUG_RA) {
- cerr << "\nAdded instructions were reordered to:\n";
+ std::cerr << "\nAdded instructions were reordered to:\n";
for(unsigned i=0; i < OrdVec.size(); i++)
- cerr << *OrdVec[i];
+ std::cerr << *OrdVec[i];
}
}
@@ -1633,7 +1632,7 @@
-void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec,
+void UltraSparcRegInfo::moveInst2OrdVec(std::vector &OrdVec,
MachineInstr *UnordInst,
PhyRegAlloc &PRA) const {
MachineOperand& UseOp = UnordInst->getOperand(0);
@@ -1645,7 +1644,7 @@
// before in the OrdVec
bool DefEqUse = false;
- std::vector::iterator OrdIt = OrdVec.begin();
+ std::vector::iterator OrdIt = OrdVec.begin();
for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
@@ -1657,7 +1656,7 @@
if( DefOp.opIsDef() &&
DefOp.getType() == MachineOperand::MO_MachineRegister) {
- //cerr << "\nDefining Ord Inst: " << *OrdInst;
+ //std::cerr << "\nDefining Ord Inst: " << *OrdInst;
if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
@@ -1678,9 +1677,9 @@
PRA.MF.getInfo()->pushTempValue(getSpilledRegSize(RegType));
// Save the UReg (%ox) on stack before it's destroyed
- vector mvec;
+ std::vector mvec;
cpReg2MemMI(mvec, UReg, getFramePointer(), StackOff, RegType);
- for (vector::iterator MI=mvec.begin();
+ for (std::vector::iterator MI=mvec.begin();
MI != mvec.end(); ++MI)
OrdIt = 1+OrdVec.insert(OrdIt, *MI);
@@ -1693,14 +1692,14 @@
cpMem2RegMI(OrdVec, getFramePointer(), StackOff, DReg, RegType);
if( DEBUG_RA ) {
- cerr << "\nFixed CIRCULAR references by reordering:";
- cerr << "\nBefore CIRCULAR Reordering:\n";
- cerr << *UnordInst;
- cerr << *OrdInst;
+ std::cerr << "\nFixed CIRCULAR references by reordering:";
+ std::cerr << "\nBefore CIRCULAR Reordering:\n";
+ std::cerr << *UnordInst;
+ std::cerr << *OrdInst;
- cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
+ std::cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
for(unsigned i=0; i < OrdVec.size(); i++)
- cerr << *(OrdVec[i]);
+ std::cerr << *(OrdVec[i]);
}
// Do not copy the UseInst to OrdVec
@@ -1717,7 +1716,7 @@
// We didn't find a def in the OrdVec, so just append this inst
OrdVec.push_back( UnordInst );
- //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
+ //std::cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
}
}// if the operand in UnordInst is a use
From brukman at cs.uiuc.edu Wed May 21 13:06:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed May 21 13:06:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
Message-ID: <200305211805.NAA16021@zion.cs.uiuc.edu>
Changes in directory llvm/lib/Target/Sparc:
SparcRegClassInfo.cpp updated: 1.19 -> 1.20
---
Log message:
Cleaned up code layout, spacing, etc. for readability purposes and to be more
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.19 llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.20
--- llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.19 Wed May 21 12:59:06 2003
+++ llvm/lib/Target/Sparc/SparcRegClassInfo.cpp Wed May 21 13:05:35 2003
@@ -26,33 +26,26 @@
{
LiveRange *LR = Node->getParentLR();
- if( DEBUG_RA ) {
+ if (DEBUG_RA) {
std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:";
printSet(*LR);
}
- if( LR->hasSuggestedColor() ) {
-
+ if (LR->hasSuggestedColor()) {
unsigned SugCol = LR->getSuggestedColor();
-
if (!IsColorUsedArr[SugCol]) {
-
- if( LR->isSuggestedColorUsable() ) {
-
+ if (LR->isSuggestedColorUsable()) {
// if the suggested color is volatile, we should use it only if
// there are no call interferences. Otherwise, it will get spilled.
-
if (DEBUG_RA)
std::cerr << "\n -Coloring with sug color: " << SugCol;
- LR->setColor( LR->getSuggestedColor() );
+ LR->setColor(LR->getSuggestedColor());
return;
+ } else if(DEBUG_RA) {
+ std::cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
}
- else if(DEBUG_RA)
- std::cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
-
- }
- else if (DEBUG_RA) { // can't allocate the suggested col
+ } else if (DEBUG_RA) { // can't allocate the suggested col
std::cerr << "\n Could NOT allocate the suggested color (already used) ";
printSet(*LR); std::cerr << "\n";
}
@@ -62,12 +55,10 @@
bool ColorFound= false; // have we found a color yet?
//if this Node is between calls
- if( ! LR->isCallInterference() ) {
-
+ if (! LR->isCallInterference()) {
// start with volatiles (we can allocate volatiles safely)
SearchStart = SparcIntRegClass::StartOfAllRegs;
- }
- else {
+ } else {
// start with non volatiles (no non-volatiles)
SearchStart = SparcIntRegClass::StartOfNonVolatileRegs;
}
@@ -75,11 +66,14 @@
unsigned c=0; // color
// find first unused color
- for( c=SearchStart; c < SparcIntRegClass::NumOfAvailRegs; c++) {
- if(!IsColorUsedArr[c] ) { ColorFound = true; break; }
+ for (c=SearchStart; c < SparcIntRegClass::NumOfAvailRegs; c++) {
+ if (!IsColorUsedArr[c]) {
+ ColorFound = true;
+ break;
+ }
}
- if( ColorFound) {
+ if (ColorFound) {
LR->setColor(c); // first color found in preffered order
if (DEBUG_RA) std::cerr << "\n Colored after first search with col " << c;
}
@@ -87,24 +81,26 @@
// if color is not found because of call interference
// try even finding a volatile color and insert save across calls
//
- else if( LR->isCallInterference() )
- {
+ else if (LR->isCallInterference()) {
// start from 0 - try to find even a volatile this time
SearchStart = SparcIntRegClass::StartOfAllRegs;
// find first unused volatile color
for(c=SearchStart; c < SparcIntRegClass::StartOfNonVolatileRegs; c++) {
- if( ! IsColorUsedArr[ c ] ) { ColorFound = true; break; }
+ if (! IsColorUsedArr[c]) {
+ ColorFound = true;
+ break;
+ }
}
if (ColorFound) {
- LR->setColor(c);
- // get the live range corresponding to live var
- // since LR span across calls, must save across calls
- //
- LR->markForSaveAcrossCalls();
- if (DEBUG_RA)
- std::cerr << "\n Colored after SECOND search with col " << c;
+ LR->setColor(c);
+ // get the live range corresponding to live var
+ // since LR span across calls, must save across calls
+ //
+ LR->markForSaveAcrossCalls();
+ if (DEBUG_RA)
+ std::cerr << "\n Colored after SECOND search with col " << c;
}
}
@@ -117,10 +113,6 @@
}
-
-
-
-
//-----------------------------------------------------------------------------
// Float Register Class - method for coloring a node in the interference graph.
//
@@ -150,17 +142,17 @@
IGNode *NeighIGNode = Node->getAdjIGNode(n);
LiveRange *NeighLR = NeighIGNode->getParentLR();
- if( NeighLR->hasColor() &&
+ if (NeighLR->hasColor() &&
NeighLR->getType() == Type::DoubleTy) {
IsColorUsedArr[ (NeighLR->getColor()) + 1 ] = true;
} else if (NeighLR->hasSuggestedColor() &&
NeighLR-> isSuggestedColorUsable() ) {
- // if the neighbour can use the suggested color
- IsColorUsedArr[ NeighLR->getSuggestedColor() ] = true;
- if (NeighLR->getType() == Type::DoubleTy)
- IsColorUsedArr[ (NeighLR->getSuggestedColor()) + 1 ] = true;
+ // if the neighbour can use the suggested color
+ IsColorUsedArr[ NeighLR->getSuggestedColor() ] = true;
+ if (NeighLR->getType() == Type::DoubleTy)
+ IsColorUsedArr[ (NeighLR->getSuggestedColor()) + 1 ] = true;
}
}
@@ -190,9 +182,8 @@
//
if (LR->getType() == Type::DoubleTy)
ColorFound = findFloatColor( LR, 32, 64, IsColorUsedArr );
-
- if( ColorFound >= 0 ) { // if we could find a color
+ if (ColorFound >= 0) { // if we could find a color
LR->setColor(ColorFound);
return;
} else {
@@ -204,36 +195,30 @@
unsigned SearchStart; // start pos of color in pref-order
//if this Node is between calls (i.e., no call interferences )
- if( ! isCallInterf ) {
+ if (! isCallInterf) {
// start with volatiles (we can allocate volatiles safely)
SearchStart = SparcFloatRegClass::StartOfAllRegs;
- }
- else {
+ } else {
// start with non volatiles (no non-volatiles)
SearchStart = SparcFloatRegClass::StartOfNonVolatileRegs;
}
- ColorFound = findFloatColor( LR, SearchStart, 32, IsColorUsedArr );
+ ColorFound = findFloatColor(LR, SearchStart, 32, IsColorUsedArr);
}
-
-
- if( ColorFound >= 0 ) { // if we could find a color
+ if (ColorFound >= 0) { // if we could find a color
LR->setColor(ColorFound);
return;
- }
- else if( isCallInterf ) {
-
+ } else if (isCallInterf) {
// We are here because there is a call interference and no non-volatile
// color could be found.
// Now try to allocate even a volatile color
-
- ColorFound = findFloatColor( LR, SparcFloatRegClass::StartOfAllRegs,
+ ColorFound = findFloatColor(LR, SparcFloatRegClass::StartOfAllRegs,
SparcFloatRegClass::StartOfNonVolatileRegs,
IsColorUsedArr);
}
- if( ColorFound >= 0 ) {
+ if (ColorFound >= 0) {
LR->setColor(ColorFound); // first color found in prefered order
LR->markForSaveAcrossCalls();
} else {
@@ -249,10 +234,10 @@
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
-int SparcFloatRegClass::findFloatColor
-(const LiveRange *LR,
- unsigned Start, unsigned End,
- std::vector &IsColorUsedArr) const
+int SparcFloatRegClass::findFloatColor(const LiveRange *LR,
+ unsigned Start,
+ unsigned End,
+ std::vector &IsColorUsedArr) const
{
bool ColorFound = false;
unsigned c;
From lattner at cs.uiuc.edu Wed May 21 13:09:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 13:09:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/TargetData.cpp
Message-ID: <200305211808.NAA30893@apoc.cs.uiuc.edu>
Changes in directory llvm/lib/Target:
TargetData.cpp updated: 1.31 -> 1.32
---
Log message:
* Fix divide by zero error with empty structs
* Empty structs should have ALIGNMENT 1, not SIZE 1.
---
Diffs of the changes:
Index: llvm/lib/Target/TargetData.cpp
diff -u llvm/lib/Target/TargetData.cpp:1.31 llvm/lib/Target/TargetData.cpp:1.32
--- llvm/lib/Target/TargetData.cpp:1.31 Sat Apr 26 15:10:58 2003
+++ llvm/lib/Target/TargetData.cpp Wed May 21 13:08:44 2003
@@ -56,15 +56,13 @@
StructSize += TySize; // Consume space for this data item
}
+ // Empty structures have alignment of 1 byte.
+ if (StructAlignment == 0) StructAlignment = 1;
+
// Add padding to the end of the struct so that it could be put in an array
// and all array elements would be aligned correctly.
if (StructSize % StructAlignment != 0)
StructSize = (StructSize/StructAlignment + 1) * StructAlignment;
-
- if (StructSize == 0) {
- StructSize = 1; // Empty struct is 1 byte
- StructAlignment = 1;
- }
}
Annotation *TargetData::TypeAnFactory(AnnotationID AID, const Annotable *T,
From lattner at cs.uiuc.edu Wed May 21 13:12:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 13:12:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/C++Frontend/2003-05-21-BitfieldHandling.c
Message-ID: <200305211811.NAA31094@apoc.cs.uiuc.edu>
Changes in directory llvm/test/Regression/C++Frontend:
2003-05-21-BitfieldHandling.c added (r1.1)
---
Log message:
New testcase
---
Diffs of the changes:
Index: llvm/test/Regression/C++Frontend/2003-05-21-BitfieldHandling.c
diff -c /dev/null llvm/test/Regression/C++Frontend/2003-05-21-BitfieldHandling.c:1.1
*** /dev/null Wed May 21 13:11:03 2003
--- llvm/test/Regression/C++Frontend/2003-05-21-BitfieldHandling.c Wed May 21 13:10:53 2003
***************
*** 0 ****
--- 1,59 ----
+ struct test_empty {
+ } e;
+ int Esize = sizeof(e);
+
+ struct rtx_def {
+ unsigned short code;
+ long long :3;
+ int mode : 8;
+ long long :0;
+ long long x :31;
+ //long long y:31;
+ } N = {2, 7, 1 };
+ int Nsize = sizeof(N); // Size = 8
+
+ struct test1 {
+ char x:1;
+ long long :0;
+ } F1; int F1size = sizeof(F1); // Size = 4
+
+ struct test2 {
+ long long x :4;
+ } F2; int F2size = sizeof(F2); // Size = 4
+
+ struct test3 {
+ char x:1;
+ long long :20;
+ } F3; int F3size = sizeof(F3); // Size = 3
+
+ struct test4 {
+ char x:1;
+ long long :21;
+ short Y : 14;
+ } F4; int F4size = sizeof(F4); // Size = 6
+
+ struct test5 {
+ char x:1;
+ long long :17;
+ char Y : 1;
+ } F5; int F5size = sizeof(F5); // Size = 3
+
+ struct test6 {
+ char x:1;
+ long long :42;
+ int Y : 21;
+ } F6; int F6size = sizeof(F6); // Size = 8
+
+ struct test {
+ char c;
+ char d : 3;
+ char e: 3;
+ int : 0;
+ char f;
+ char :0;
+ long long x : 4;
+ } M; int Msize = sizeof(M); // Size = 8
+
+ int main() {
+ return 0;
+ }
From brukman at cs.uiuc.edu Wed May 21 13:49:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed May 21 13:49:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcInstrInfo.cpp SparcInstrSelection.cpp
Message-ID: <200305211848.NAA16130@zion.cs.uiuc.edu>
Changes in directory llvm/lib/Target/Sparc:
SparcInstrInfo.cpp updated: 1.41 -> 1.42
SparcInstrSelection.cpp updated: 1.90 -> 1.91
---
Log message:
Cleaned up code layout, spacing, etc. for readability purposes and to be more
consistent with the style of LLVM's code base (and itself! it's inconsistent in
some places.)
No functional changes were made.
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcInstrInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.41 llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.42
--- llvm/lib/Target/Sparc/SparcInstrInfo.cpp:1.41 Tue May 20 15:32:23 2003
+++ llvm/lib/Target/Sparc/SparcInstrInfo.cpp Wed May 21 13:48:06 2003
@@ -97,31 +97,28 @@
bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
// Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
- if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
- {
- miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
- miSETHI->setOperandHi32(0);
- mvec.push_back(miSETHI);
- }
+ if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
+ miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
+ miSETHI->setOperandHi32(0);
+ mvec.push_back(miSETHI);
+ }
// Set the low 10 or 12 bits in dest. This is necessary if no SETHI
// was generated, or if the low 10 bits are non-zero.
- if (miSETHI==NULL || C & MAXLO)
- {
- if (miSETHI)
- { // unsigned value with high-order bits set using SETHI
- miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
- miOR->setOperandLo32(1);
- }
- else
- { // unsigned or small signed value that fits in simm13 field of OR
- assert(smallNegValue || (C & ~MAXSIMM) == 0);
- miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
- .getZeroRegNum())
- .addSImm(sC).addRegDef(dest);
- }
- mvec.push_back(miOR);
+ if (miSETHI==NULL || C & MAXLO) {
+ if (miSETHI) {
+ // unsigned value with high-order bits set using SETHI
+ miOR = BuildMI(V9::OR,3).addReg(dest).addZImm(C).addRegDef(dest);
+ miOR->setOperandLo32(1);
+ } else {
+ // unsigned or small signed value that fits in simm13 field of OR
+ assert(smallNegValue || (C & ~MAXSIMM) == 0);
+ miOR = BuildMI(V9::OR, 3).addMReg(target.getRegInfo()
+ .getZeroRegNum())
+ .addSImm(sC).addRegDef(dest);
}
+ mvec.push_back(miOR);
+ }
assert((miSETHI || miOR) && "Oops, no code was generated!");
}
@@ -266,17 +263,16 @@
static const uint64_t lo32 = (uint32_t) ~0;
if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
CreateSETUWConst(target, (uint32_t) C, dest, mvec);
- else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
- { // All high 33 (not 32) bits are 1s: sign-extension will take care
- // of high 32 bits, so use the sequence for signed int
- CreateSETSWConst(target, (int32_t) C, dest, mvec);
- }
- else if (C > lo32)
- { // C does not fit in 32 bits
- TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
- mcfi.addTemp(tmpReg);
- CreateSETXConst(target, C, tmpReg, dest, mvec);
- }
+ else if ((C & ~lo32) == ~lo32 && (C & (1 << 31))) {
+ // All high 33 (not 32) bits are 1s: sign-extension will take care
+ // of high 32 bits, so use the sequence for signed int
+ CreateSETSWConst(target, (int32_t) C, dest, mvec);
+ } else if (C > lo32) {
+ // C does not fit in 32 bits
+ TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
+ mcfi.addTemp(tmpReg);
+ CreateSETXConst(target, C, tmpReg, dest, mvec);
+ }
}
@@ -425,80 +421,72 @@
if (isa(val))
val = cast(val)->getValue();
- if (isa(val))
- {
+ if (isa(val)) {
TmpInstruction* tmpReg =
new TmpInstruction(PointerType::get(val->getType()), val);
mcfi.addTemp(tmpReg);
CreateSETXLabel(target, val, tmpReg, dest, mvec);
- }
- else if (valType->isIntegral())
- {
- bool isValidConstant;
- unsigned opSize = target.getTargetData().getTypeSize(val->getType());
- unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
+ } else if (valType->isIntegral()) {
+ bool isValidConstant;
+ unsigned opSize = target.getTargetData().getTypeSize(val->getType());
+ unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
- if (! dest->getType()->isSigned())
- {
- uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
- assert(isValidConstant && "Unrecognized constant");
-
- if (opSize > destSize || (val->getType()->isSigned() && destSize < 8))
- { // operand is larger than dest,
- // OR both are equal but smaller than the full register size
- // AND operand is signed, so it may have extra sign bits:
- // mask high bits
- C = C & ((1U << 8*destSize) - 1);
- }
- CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
- }
- else
- {
- int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
- assert(isValidConstant && "Unrecognized constant");
-
- if (opSize > destSize)
- // operand is larger than dest: mask high bits
- C = C & ((1U << 8*destSize) - 1);
-
- if (opSize > destSize ||
- (opSize == destSize && !val->getType()->isSigned()))
- // sign-extend from destSize to 64 bits
- C = ((C & (1U << (8*destSize - 1)))
- ? C | ~((1U << 8*destSize) - 1)
- : C);
+ if (! dest->getType()->isSigned()) {
+ uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
+ assert(isValidConstant && "Unrecognized constant");
+
+ if (opSize > destSize || (val->getType()->isSigned() && destSize < 8)) {
+ // operand is larger than dest,
+ // OR both are equal but smaller than the full register size
+ // AND operand is signed, so it may have extra sign bits:
+ // mask high bits
+ C = C & ((1U << 8*destSize) - 1);
+ }
+ CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
+ } else {
+ int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
+ assert(isValidConstant && "Unrecognized constant");
+
+ if (opSize > destSize)
+ // operand is larger than dest: mask high bits
+ C = C & ((1U << 8*destSize) - 1);
+
+ if (opSize > destSize ||
+ (opSize == destSize && !val->getType()->isSigned()))
+ // sign-extend from destSize to 64 bits
+ C = ((C & (1U << (8*destSize - 1)))
+ ? C | ~((1U << 8*destSize) - 1)
+ : C);
- CreateIntSetInstruction(target, C, dest, mvec, mcfi);
- }
+ CreateIntSetInstruction(target, C, dest, mvec, mcfi);
}
- else
- {
- // Make an instruction sequence to load the constant, viz:
- // SETX , tmpReg, addrReg
- // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
+ } else {
+ // Make an instruction sequence to load the constant, viz:
+ // SETX , tmpReg, addrReg
+ // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
- // First, create a tmp register to be used by the SETX sequence.
- TmpInstruction* tmpReg =
- new TmpInstruction(PointerType::get(val->getType()), val);
- mcfi.addTemp(tmpReg);
+ // First, create a tmp register to be used by the SETX sequence.
+ TmpInstruction* tmpReg =
+ new TmpInstruction(PointerType::get(val->getType()), val);
+ mcfi.addTemp(tmpReg);
- // Create another TmpInstruction for the address register
- TmpInstruction* addrReg =
- new TmpInstruction(PointerType::get(val->getType()), val);
- mcfi.addTemp(addrReg);
+ // Create another TmpInstruction for the address register
+ TmpInstruction* addrReg =
+ new TmpInstruction(PointerType::get(val->getType()), val);
+ mcfi.addTemp(addrReg);
- // Put the address (a symbolic name) into a register
- CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
+ // Put the address (a symbolic name) into a register
+ CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
- // Generate the load instruction
- int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
- unsigned Opcode = ChooseLoadInstruction(val->getType());
- mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
- addSImm(zeroOffset).addRegDef(dest));
+ // Generate the load instruction
+ int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
+ unsigned Opcode = ChooseLoadInstruction(val->getType());
+ mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
+ addSImm(zeroOffset).addRegDef(dest));
- // Make sure constant is emitted to constant pool in assembly code.
- MachineFunction::get(F).getInfo()->addToConstantPool(cast(val));
- }
+ // Make sure constant is emitted to constant pool in assembly code.
+ MachineFunction::get(F).getInfo()->addToConstantPool(cast(val));
+ }
}
@@ -535,16 +523,16 @@
// Note that the store instruction is the same for signed and unsigned ints.
const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
Value* storeVal = val;
- if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy))
- { // sign- or zero-extend respectively
- storeVal = new TmpInstruction(storeType, val);
- if (val->getType()->isSigned())
- CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
- mvec, mcfi);
- else
- CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
- mvec, mcfi);
- }
+ if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
+ // sign- or zero-extend respectively
+ storeVal = new TmpInstruction(storeType, val);
+ if (val->getType()->isSigned())
+ CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
+ mvec, mcfi);
+ else
+ CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
+ mvec, mcfi);
+ }
unsigned FPReg = target.getRegInfo().getFramePointer();
mvec.push_back(BuildMI(ChooseStoreInstruction(storeType), 3)
@@ -622,8 +610,7 @@
const Type* resultType = dest->getType();
MachineOpCode opCode = ChooseAddInstructionByType(resultType);
- if (opCode == V9::INVALID_OPCODE)
- {
+ if (opCode == V9::INVALID_OPCODE) {
assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
return;
}
@@ -632,8 +619,7 @@
// a global variable (i.e., a constant address), generate a load
// instruction instead of an add
//
- if (isa(src))
- {
+ if (isa(src)) {
unsigned int machineRegNum;
int64_t immedValue;
MachineOperand::MachineOperandType opType =
@@ -646,14 +632,13 @@
else if (isa(src))
loadConstantToReg = true;
- if (loadConstantToReg)
- { // `src' is constant and cannot fit in immed field for the ADD
+ if (loadConstantToReg) {
+ // `src' is constant and cannot fit in immed field for the ADD
// Insert instructions to "load" the constant into a register
target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
mvec, mcfi);
- }
- else
- { // Create an add-with-0 instruction of the appropriate type.
+ } else {
+ // Create an add-with-0 instruction of the appropriate type.
// Make `src' the second operand, in case it is a constant
// Use (unsigned long) 0 for a NULL pointer value.
//
@@ -682,8 +667,8 @@
assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
- if (numLowBits < 32)
- { // SLL is needed since operand size is < 32 bits.
+ if (numLowBits < 32) {
+ // SLL is needed since operand size is < 32 bits.
TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
srcVal, destVal, "make32");
mcfi.addTemp(tmpI);
Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.90 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.91
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.90 Wed May 21 12:59:06 2003
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp Wed May 21 13:48:06 2003
@@ -97,50 +97,49 @@
InstructionNode* ptrChild = gepNode;
while (ptrChild && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
ptrChild->getOpLabel() == GetElemPtrIdx))
- {
- // Child is a GetElemPtr instruction
- gepInst = cast(ptrChild->getValue());
- User::op_iterator OI, firstIdx = gepInst->idx_begin();
- User::op_iterator lastIdx = gepInst->idx_end();
- bool allConstantOffsets = true;
-
- // The first index of every GEP must be an array index.
- assert((*firstIdx)->getType() == Type::LongTy &&
- "INTERNAL ERROR: Structure index for a pointer type!");
-
- // If the last instruction had a leading non-zero index, check if the
- // current one references a sequential (i.e., indexable) type.
- // If not, the code is not type-safe and we would create an illegal GEP
- // by folding them, so don't fold any more instructions.
- //
- if (lastInstHasLeadingNonZero)
- if (! isa(gepInst->getType()->getElementType()))
- break; // cannot fold in any preceding getElementPtr instrs.
-
- // Check that all offsets are constant for this instruction
- for (OI = firstIdx; allConstantOffsets && OI != lastIdx; ++OI)
- allConstantOffsets = isa(*OI);
-
- if (allConstantOffsets)
- { // Get pointer value out of ptrChild.
- ptrVal = gepInst->getPointerOperand();
-
- // Remember if it has leading zero index: it will be discarded later.
- lastInstHasLeadingNonZero = ! IsZero(*firstIdx);
-
- // Insert its index vector at the start, skipping any leading [0]
- chainIdxVec.insert(chainIdxVec.begin(),
- firstIdx + !lastInstHasLeadingNonZero, lastIdx);
-
- // Mark the folded node so no code is generated for it.
- ((InstructionNode*) ptrChild)->markFoldedIntoParent();
-
- // Get the previous GEP instruction and continue trying to fold
- ptrChild = dyn_cast(ptrChild->leftChild());
- }
- else // cannot fold this getElementPtr instr. or any preceding ones
- break;
- }
+ {
+ // Child is a GetElemPtr instruction
+ gepInst = cast(ptrChild->getValue());
+ User::op_iterator OI, firstIdx = gepInst->idx_begin();
+ User::op_iterator lastIdx = gepInst->idx_end();
+ bool allConstantOffsets = true;
+
+ // The first index of every GEP must be an array index.
+ assert((*firstIdx)->getType() == Type::LongTy &&
+ "INTERNAL ERROR: Structure index for a pointer type!");
+
+ // If the last instruction had a leading non-zero index, check if the
+ // current one references a sequential (i.e., indexable) type.
+ // If not, the code is not type-safe and we would create an illegal GEP
+ // by folding them, so don't fold any more instructions.
+ //
+ if (lastInstHasLeadingNonZero)
+ if (! isa(gepInst->getType()->getElementType()))
+ break; // cannot fold in any preceding getElementPtr instrs.
+
+ // Check that all offsets are constant for this instruction
+ for (OI = firstIdx; allConstantOffsets && OI != lastIdx; ++OI)
+ allConstantOffsets = isa(*OI);
+
+ if (allConstantOffsets) {
+ // Get pointer value out of ptrChild.
+ ptrVal = gepInst->getPointerOperand();
+
+ // Remember if it has leading zero index: it will be discarded later.
+ lastInstHasLeadingNonZero = ! IsZero(*firstIdx);
+
+ // Insert its index vector at the start, skipping any leading [0]
+ chainIdxVec.insert(chainIdxVec.begin(),
+ firstIdx + !lastInstHasLeadingNonZero, lastIdx);
+
+ // Mark the folded node so no code is generated for it.
+ ((InstructionNode*) ptrChild)->markFoldedIntoParent();
+
+ // Get the previous GEP instruction and continue trying to fold
+ ptrChild = dyn_cast(ptrChild->leftChild());
+ } else // cannot fold this getElementPtr instr. or any preceding ones
+ break;
+ }
// If the first getElementPtr instruction had a leading [0], add it back.
// Note that this instruction is the *last* one successfully folded above.
@@ -186,11 +185,10 @@
bool foldedGEPs = false;
bool leadingNonZeroIdx = gepI && ! IsZero(*gepI->idx_begin());
if (allConstantIndices)
- if (Value* newPtr = FoldGetElemChain(ptrChild, idxVec, leadingNonZeroIdx))
- {
- ptrVal = newPtr;
- foldedGEPs = true;
- }
+ if (Value* newPtr = FoldGetElemChain(ptrChild, idxVec, leadingNonZeroIdx)) {
+ ptrVal = newPtr;
+ foldedGEPs = true;
+ }
// Append the index vector of the current instruction.
// Skip the leading [0] index if preceding GEPs were folded into this.
@@ -242,12 +240,12 @@
InstructionNode* gepNode = NULL;
if (isa(memInst))
gepNode = memInstrNode;
- else if (isa(ptrChild) && isa(ptrVal))
- { // Child of load/store is a GEP and memInst is its only use.
- // Use its indices and mark it as folded.
- gepNode = cast(ptrChild);
- gepNode->markFoldedIntoParent();
- }
+ else if (isa(ptrChild) && isa(ptrVal)) {
+ // Child of load/store is a GEP and memInst is its only use.
+ // Use its indices and mark it as folded.
+ gepNode = cast(ptrChild);
+ gepNode->markFoldedIntoParent();
+ }
// If there are no indices, return the current pointer.
// Else extract the pointer from the GEP and fold the indices.
@@ -268,18 +266,18 @@
((InstructionNode*) instrNode->leftChild())->getInstruction();
switch(setCCInstr->getOpcode())
- {
- case Instruction::SetEQ: opCode = V9::BRZ; break;
- case Instruction::SetNE: opCode = V9::BRNZ; break;
- case Instruction::SetLE: opCode = V9::BRLEZ; break;
- case Instruction::SetGE: opCode = V9::BRGEZ; break;
- case Instruction::SetLT: opCode = V9::BRLZ; break;
- case Instruction::SetGT: opCode = V9::BRGZ; break;
- default:
- assert(0 && "Unrecognized VM instruction!");
- opCode = V9::INVALID_OPCODE;
- break;
- }
+ {
+ case Instruction::SetEQ: opCode = V9::BRZ; break;
+ case Instruction::SetNE: opCode = V9::BRNZ; break;
+ case Instruction::SetLE: opCode = V9::BRLEZ; break;
+ case Instruction::SetGE: opCode = V9::BRGEZ; break;
+ case Instruction::SetLT: opCode = V9::BRLZ; break;
+ case Instruction::SetGT: opCode = V9::BRGZ; break;
+ default:
+ assert(0 && "Unrecognized VM instruction!");
+ opCode = V9::INVALID_OPCODE;
+ break;
+ }
return opCode;
}
@@ -293,36 +291,33 @@
bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
- if (isSigned)
+ if (isSigned) {
+ switch(setCCInstr->getOpcode())
{
- switch(setCCInstr->getOpcode())
- {
- case Instruction::SetEQ: opCode = V9::BE; break;
- case Instruction::SetNE: opCode = V9::BNE; break;
- case Instruction::SetLE: opCode = V9::BLE; break;
- case Instruction::SetGE: opCode = V9::BGE; break;
- case Instruction::SetLT: opCode = V9::BL; break;
- case Instruction::SetGT: opCode = V9::BG; break;
- default:
- assert(0 && "Unrecognized VM instruction!");
- break;
- }
+ case Instruction::SetEQ: opCode = V9::BE; break;
+ case Instruction::SetNE: opCode = V9::BNE; break;
+ case Instruction::SetLE: opCode = V9::BLE; break;
+ case Instruction::SetGE: opCode = V9::BGE; break;
+ case Instruction::SetLT: opCode = V9::BL; break;
+ case Instruction::SetGT: opCode = V9::BG; break;
+ default:
+ assert(0 && "Unrecognized VM instruction!");
+ break;
}
- else
+ } else {
+ switch(setCCInstr->getOpcode())
{
- switch(setCCInstr->getOpcode())
- {
- case Instruction::SetEQ: opCode = V9::BE; break;
- case Instruction::SetNE: opCode = V9::BNE; break;
- case Instruction::SetLE: opCode = V9::BLEU; break;
- case Instruction::SetGE: opCode = V9::BCC; break;
- case Instruction::SetLT: opCode = V9::BCS; break;
- case Instruction::SetGT: opCode = V9::BGU; break;
- default:
- assert(0 && "Unrecognized VM instruction!");
- break;
- }
+ case Instruction::SetEQ: opCode = V9::BE; break;
+ case Instruction::SetNE: opCode = V9::BNE; break;
+ case Instruction::SetLE: opCode = V9::BLEU; break;
+ case Instruction::SetGE: opCode = V9::BCC; break;
+ case Instruction::SetLT: opCode = V9::BCS; break;
+ case Instruction::SetGT: opCode = V9::BGU; break;
+ default:
+ assert(0 && "Unrecognized VM instruction!");
+ break;
}
+ }
return opCode;
}
@@ -334,17 +329,17 @@
MachineOpCode opCode = V9::INVALID_OPCODE;
switch(setCCInstr->getOpcode())
- {
- case Instruction::SetEQ: opCode = V9::FBE; break;
- case Instruction::SetNE: opCode = V9::FBNE; break;
- case Instruction::SetLE: opCode = V9::FBLE; break;
- case Instruction::SetGE: opCode = V9::FBGE; break;
- case Instruction::SetLT: opCode = V9::FBL; break;
- case Instruction::SetGT: opCode = V9::FBG; break;
- default:
- assert(0 && "Unrecognized VM instruction!");
- break;
- }
+ {
+ case Instruction::SetEQ: opCode = V9::FBE; break;
+ case Instruction::SetNE: opCode = V9::FBNE; break;
+ case Instruction::SetLE: opCode = V9::FBLE; break;
+ case Instruction::SetGE: opCode = V9::FBGE; break;
+ case Instruction::SetLT: opCode = V9::FBL; break;
+ case Instruction::SetGT: opCode = V9::FBG; break;
+ default:
+ assert(0 && "Unrecognized VM instruction!");
+ break;
+ }
return opCode;
}
@@ -367,11 +362,10 @@
assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
- if (lastFunction != F)
- {
- lastFunction = F;
- boolToTmpCache.clear();
- }
+ if (lastFunction != F) {
+ lastFunction = F;
+ boolToTmpCache.clear();
+ }
// Look for tmpI and create a new one otherwise. The new value is
// directly written to map using the ref returned by operator[].
@@ -407,17 +401,17 @@
MachineOpCode opCode = V9::INVALID_OPCODE;
switch(instrNode->getInstruction()->getOpcode())
- {
- case Instruction::SetEQ: opCode = V9::MOVFE; break;
- case Instruction::SetNE: opCode = V9::MOVFNE; break;
- case Instruction::SetLE: opCode = V9::MOVFLE; break;
- case Instruction::SetGE: opCode = V9::MOVFGE; break;
- case Instruction::SetLT: opCode = V9::MOVFL; break;
- case Instruction::SetGT: opCode = V9::MOVFG; break;
- default:
- assert(0 && "Unrecognized VM instruction!");
- break;
- }
+ {
+ case Instruction::SetEQ: opCode = V9::MOVFE; break;
+ case Instruction::SetNE: opCode = V9::MOVFNE; break;
+ case Instruction::SetLE: opCode = V9::MOVFLE; break;
+ case Instruction::SetGE: opCode = V9::MOVFGE; break;
+ case Instruction::SetLT: opCode = V9::MOVFL; break;
+ case Instruction::SetGT: opCode = V9::MOVFG; break;
+ default:
+ assert(0 && "Unrecognized VM instruction!");
+ break;
+ }
return opCode;
}
@@ -441,15 +435,15 @@
valueToMove = 1;
switch(instrNode->getInstruction()->getOpcode())
- {
- case Instruction::SetEQ: opCode = V9::MOVE; break;
- case Instruction::SetLE: opCode = V9::MOVLE; break;
- case Instruction::SetGE: opCode = V9::MOVGE; break;
- case Instruction::SetLT: opCode = V9::MOVL; break;
- case Instruction::SetGT: opCode = V9::MOVG; break;
- case Instruction::SetNE: assert(0 && "No move required!"); break;
- default: assert(0 && "Unrecognized VM instr!"); break;
- }
+ {
+ case Instruction::SetEQ: opCode = V9::MOVE; break;
+ case Instruction::SetLE: opCode = V9::MOVLE; break;
+ case Instruction::SetGE: opCode = V9::MOVGE; break;
+ case Instruction::SetLT: opCode = V9::MOVL; break;
+ case Instruction::SetGT: opCode = V9::MOVG; break;
+ case Instruction::SetNE: assert(0 && "No move required!"); break;
+ default: assert(0 && "Unrecognized VM instr!"); break;
+ }
return opCode;
}
@@ -460,41 +454,42 @@
MachineOpCode opCode = V9::INVALID_OPCODE;
switch(vopCode)
- {
- case ToFloatTy:
- if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
- opCode = V9::FITOS;
- else if (opType == Type::LongTy)
- opCode = V9::FXTOS;
- else if (opType == Type::DoubleTy)
- opCode = V9::FDTOS;
- else if (opType == Type::FloatTy)
- ;
- else
- assert(0 && "Cannot convert this type to FLOAT on SPARC");
- break;
+ {
+ case ToFloatTy:
+ if (opType == Type::SByteTy || opType == Type::ShortTy ||
+ opType == Type::IntTy)
+ opCode = V9::FITOS;
+ else if (opType == Type::LongTy)
+ opCode = V9::FXTOS;
+ else if (opType == Type::DoubleTy)
+ opCode = V9::FDTOS;
+ else if (opType == Type::FloatTy)
+ ;
+ else
+ assert(0 && "Cannot convert this type to FLOAT on SPARC");
+ break;
- case ToDoubleTy:
- // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
- // Both functions should treat the integer as a 32-bit value for types
- // of 4 bytes or less, and as a 64-bit value otherwise.
- if (opType == Type::SByteTy || opType == Type::UByteTy ||
- opType == Type::ShortTy || opType == Type::UShortTy ||
- opType == Type::IntTy || opType == Type::UIntTy)
- opCode = V9::FITOD;
- else if (opType == Type::LongTy || opType == Type::ULongTy)
- opCode = V9::FXTOD;
- else if (opType == Type::FloatTy)
- opCode = V9::FSTOD;
- else if (opType == Type::DoubleTy)
- ;
- else
- assert(0 && "Cannot convert this type to DOUBLE on SPARC");
- break;
+ case ToDoubleTy:
+ // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
+ // Both functions should treat the integer as a 32-bit value for types
+ // of 4 bytes or less, and as a 64-bit value otherwise.
+ if (opType == Type::SByteTy || opType == Type::UByteTy ||
+ opType == Type::ShortTy || opType == Type::UShortTy ||
+ opType == Type::IntTy || opType == Type::UIntTy)
+ opCode = V9::FITOD;
+ else if (opType == Type::LongTy || opType == Type::ULongTy)
+ opCode = V9::FXTOD;
+ else if (opType == Type::FloatTy)
+ opCode = V9::FSTOD;
+ else if (opType == Type::DoubleTy)
+ ;
+ else
+ assert(0 && "Cannot convert this type to DOUBLE on SPARC");
+ break;
- default:
- break;
- }
+ default:
+ break;
+ }
return opCode;
}
@@ -507,22 +502,17 @@
assert((opType == Type::FloatTy || opType == Type::DoubleTy)
&& "This function should only be called for FLOAT or DOUBLE");
- if (tid==Type::UIntTyID)
- {
- assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded"
- " into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!");
- }
- else if (tid==Type::SByteTyID || tid==Type::ShortTyID || tid==Type::IntTyID ||
- tid==Type::UByteTyID || tid==Type::UShortTyID)
- {
- opCode = (opType == Type::FloatTy)? V9::FSTOI : V9::FDTOI;
- }
- else if (tid==Type::LongTyID || tid==Type::ULongTyID)
- {
+ if (tid == Type::UIntTyID) {
+ assert(tid != Type::UIntTyID && "FP-to-uint conversions must be expanded"
+ " into FP->long->uint for SPARC v9: SO RUN PRESELECTION PASS!");
+ } else if (tid == Type::SByteTyID || tid == Type::ShortTyID ||
+ tid == Type::IntTyID || tid == Type::UByteTyID ||
+ tid == Type::UShortTyID) {
+ opCode = (opType == Type::FloatTy)? V9::FSTOI : V9::FDTOI;
+ } else if (tid == Type::LongTyID || tid == Type::ULongTyID) {
opCode = (opType == Type::FloatTy)? V9::FSTOX : V9::FDTOX;
- }
- else
- assert(0 && "Should not get here, Mo!");
+ } else
+ assert(0 && "Should not get here, Mo!");
return opCode;
}
@@ -611,11 +601,11 @@
// instead of an FADD (1 vs 3 cycles). There is no integer MOV.
//
if (ConstantFP *FPC = dyn_cast(constOp)) {
- double dval = FPC->getValue();
- if (dval == 0.0)
- minstr = CreateMovFloatInstruction(instrNode,
- instrNode->getInstruction()->getType());
- }
+ double dval = FPC->getValue();
+ if (dval == 0.0)
+ minstr = CreateMovFloatInstruction(instrNode,
+ instrNode->getInstruction()->getType());
+ }
return minstr;
}
@@ -626,18 +616,17 @@
{
MachineOpCode opCode = V9::INVALID_OPCODE;
- if (resultType->isInteger() || isa(resultType))
- {
+ if (resultType->isInteger() || isa(resultType)) {
opCode = V9::SUB;
- }
- else
+ } else {
switch(resultType->getPrimitiveID())
- {
- case Type::FloatTyID: opCode = V9::FSUBS; break;
- case Type::DoubleTyID: opCode = V9::FSUBD; break;
- default: assert(0 && "Invalid type for SUB instruction"); break;
- }
-
+ {
+ case Type::FloatTyID: opCode = V9::FSUBS; break;
+ case Type::DoubleTyID: opCode = V9::FSUBD; break;
+ default: assert(0 && "Invalid type for SUB instruction"); break;
+ }
+ }
+
return opCode;
}
From brukman at cs.uiuc.edu Wed May 21 14:35:01 2003
From: brukman at cs.uiuc.edu (Misha Brukman)
Date: Wed May 21 14:35:01 2003
Subject: [llvm-commits] CVS: llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
Message-ID: <200305211934.OAA16392@zion.cs.uiuc.edu>
Changes in directory llvm/lib/Target/Sparc:
SparcRegClassInfo.cpp updated: 1.20 -> 1.21
---
Log message:
Fixed `volatile' typo.
---
Diffs of the changes:
Index: llvm/lib/Target/Sparc/SparcRegClassInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.20 llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.21
--- llvm/lib/Target/Sparc/SparcRegClassInfo.cpp:1.20 Wed May 21 13:05:35 2003
+++ llvm/lib/Target/Sparc/SparcRegClassInfo.cpp Wed May 21 14:34:28 2003
@@ -43,7 +43,7 @@
LR->setColor(LR->getSuggestedColor());
return;
} else if(DEBUG_RA) {
- std::cerr << "\n Couldn't alloc Sug col - LR voloatile & calls interf";
+ std::cerr << "\n Couldn't alloc Sug col - LR volatile & calls interf";
}
} else if (DEBUG_RA) { // can't allocate the suggested col
std::cerr << "\n Could NOT allocate the suggested color (already used) ";
From lattner at cs.uiuc.edu Wed May 21 14:42:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 14:42:00 2003
Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExtractFunction.cpp
Message-ID: <200305211941.OAA01723@apoc.cs.uiuc.edu>
Changes in directory llvm/tools/bugpoint:
ExtractFunction.cpp updated: 1.7 -> 1.8
---
Log message:
Increase odds that this won't bork things
---
Diffs of the changes:
Index: llvm/tools/bugpoint/ExtractFunction.cpp
diff -u llvm/tools/bugpoint/ExtractFunction.cpp:1.7 llvm/tools/bugpoint/ExtractFunction.cpp:1.8
--- llvm/tools/bugpoint/ExtractFunction.cpp:1.7 Fri Apr 25 17:08:12 2003
+++ llvm/tools/bugpoint/ExtractFunction.cpp Wed May 21 14:41:31 2003
@@ -78,6 +78,11 @@
///
Module *BugDriver::performFinalCleanups() const {
Module *M = CloneModule(Program);
+
+ // Make all functions external, so GlobalDCE doesn't delete them...
+ for (Module::iterator I = M->begin(), E = M->end(); I != E; ++I)
+ I->setLinkage(GlobalValue::ExternalLinkage);
+
PassManager CleanupPasses;
CleanupPasses.add(createFunctionResolvingPass());
CleanupPasses.add(createGlobalDCEPass());
From lattner at cs.uiuc.edu Wed May 21 14:49:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 14:49:01 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll
Message-ID: <200305211948.OAA02015@apoc.cs.uiuc.edu>
Changes in directory llvm/test/Regression/Transforms/BasicAA:
2003-05-21-GEP-Problem.ll added (r1.1)
---
Log message:
New testcase identified by joel
---
Diffs of the changes:
Index: llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll
diff -c /dev/null llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll:1.1
*** /dev/null Wed May 21 14:48:43 2003
--- llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll Wed May 21 14:48:33 2003
***************
*** 0 ****
--- 1,26 ----
+ ; RUN: as < %s | opt -licm -disable-output
+ target endian = big
+ target pointersize = 64
+ %struct..apr_array_header_t = type { %struct..apr_pool_t*, int, int, int, sbyte* }
+ %struct..apr_pool_t = type opaque
+ %struct..apr_table_t = type { %struct..apr_array_header_t, uint, [32 x int], [32 x int] }
+
+ implementation ; Functions:
+
+ void %table_reindex(%struct..apr_table_t* %t.1) { ; No predecessors!
+ br label %loopentry
+
+ loopentry: ; preds = %0, %no_exit
+ %tmp.101 = getelementptr %struct..apr_table_t* %t.1, long 0, ubyte 0, ubyte 2 ; [#uses=1]
+ %tmp.11 = load int* %tmp.101 ; [#uses=0]
+ br bool false, label %no_exit, label %UnifiedExitNode
+
+ no_exit: ; preds = %loopentry
+ %tmp.25 = cast int 0 to long ; [#uses=1]
+ %tmp.261 = getelementptr %struct..apr_table_t* %t.1, long 0, ubyte 3, long %tmp.25 ; [#uses=1]
+ store int 0, int* %tmp.261
+ br label %loopentry
+
+ UnifiedExitNode: ; preds = %loopentry
+ ret void
+ }
From lattner at cs.uiuc.edu Wed May 21 14:56:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 14:56:00 2003
Subject: [llvm-commits] CVS: llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll
Message-ID: <200305211955.OAA02054@apoc.cs.uiuc.edu>
Changes in directory llvm/test/Regression/Transforms/BasicAA:
2003-05-21-GEP-Problem.ll updated: 1.1 -> 1.2
---
Log message:
Trim testcase a bit
---
Diffs of the changes:
Index: llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll
diff -u llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll:1.1 llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll:1.2
--- llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll:1.1 Wed May 21 14:48:33 2003
+++ llvm/test/Regression/Transforms/BasicAA/2003-05-21-GEP-Problem.ll Wed May 21 14:55:10 2003
@@ -1,11 +1,6 @@
; RUN: as < %s | opt -licm -disable-output
-target endian = big
-target pointersize = 64
- %struct..apr_array_header_t = type { %struct..apr_pool_t*, int, int, int, sbyte* }
- %struct..apr_pool_t = type opaque
+ %struct..apr_array_header_t = type { int*, int, int, int, sbyte* }
%struct..apr_table_t = type { %struct..apr_array_header_t, uint, [32 x int], [32 x int] }
-
-implementation ; Functions:
void %table_reindex(%struct..apr_table_t* %t.1) { ; No predecessors!
br label %loopentry
From lattner at cs.uiuc.edu Wed May 21 15:24:00 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 15:24:00 2003
Subject: [llvm-commits] CVS: llvm/lib/Analysis/BasicAliasAnalysis.cpp
Message-ID: <200305212023.PAA02271@apoc.cs.uiuc.edu>
Changes in directory llvm/lib/Analysis:
BasicAliasAnalysis.cpp updated: 1.8 -> 1.9
---
Log message:
Fix Bug: BasicAA/2003-05-21-GEP-Problem.ll
---
Diffs of the changes:
Index: llvm/lib/Analysis/BasicAliasAnalysis.cpp
diff -u llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.8 llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.9
--- llvm/lib/Analysis/BasicAliasAnalysis.cpp:1.8 Fri Apr 25 13:03:06 2003
+++ llvm/lib/Analysis/BasicAliasAnalysis.cpp Wed May 21 15:23:26 2003
@@ -290,7 +290,7 @@
if (isa(Op2))
Indices2.push_back((Value*)Op2);
else // Conservatively assume the minimum value for this index
- Indices2.push_back(Constant::getNullValue(Op1->getType()));
+ Indices2.push_back(Constant::getNullValue(Op2->getType()));
}
}
From lattner at cs.uiuc.edu Wed May 21 15:40:01 2003
From: lattner at cs.uiuc.edu (Chris Lattner)
Date: Wed May 21 15:40:01 2003
Subject: [llvm-commits] CVS: llvm/tools/bugpoint/ExtractFunction.cpp
Message-ID: <200305212039.PAA02937@apoc.cs.uiuc.edu>
Changes in directory llvm/tools/bugpoint:
ExtractFunction.cpp updated: 1.8 -> 1.9
---
Log message:
Allow disabling final cleanups
---
Diffs of the changes:
Index: llvm/tools/bugpoint/ExtractFunction.cpp
diff -u llvm/tools/bugpoint/ExtractFunction.cpp:1.8 llvm/tools/bugpoint/ExtractFunction.cpp:1.9
--- llvm/tools/bugpoint/ExtractFunction.cpp:1.8 Wed May 21 14:41:31 2003
+++ llvm/tools/bugpoint/ExtractFunction.cpp Wed May 21 15:38:59 2003
@@ -26,6 +26,9 @@
cl::opt
|