[llvm-commits] CVS: llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h Phases.cpp SparcInstManip.cpp SparcInstManip.h
Joel Stanley
jstanley at cs.uiuc.edu
Tue May 13 12:31:51 PDT 2003
Changes in directory llvm/lib/Reoptimizer/Inst/lib:
PhaseInfo.h updated: 1.5 -> 1.6
Phases.cpp updated: 1.27 -> 1.28
SparcInstManip.cpp updated: 1.7 -> 1.8
SparcInstManip.h updated: 1.8 -> 1.9
---
Log message:
Now using heap-allocated temps to transfer values between start- and
end-interval sites. This only affects phases 4 and 5.
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h
diff -u llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h:1.5 llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h:1.6
--- llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h:1.5 Mon May 12 21:00:22 2003
+++ llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h Tue May 13 12:29:49 2003
@@ -15,10 +15,12 @@
#define DEBUG 1
#if DEBUG
-#define VERBOSE 1
+#define VERBOSE 2
#define DEBUG_MSG(v, x) if(VERBOSE >= v) std::cerr << x
+#define HEX(x) std::hex << x << std::dec
#else
#define DEBUG_MSG(v, x)
+#define HEX(x)
#endif
typedef std::pair<uint64_t, uint64_t> AddressRange;
@@ -28,6 +30,7 @@
unsigned short* loadVar;
unsigned gbtStartIdx;
unsigned paramSize;
+ void* paramMem;
void* instFunc;
};
Index: llvm/lib/Reoptimizer/Inst/lib/Phases.cpp
diff -u llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.27 llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.28
--- llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.27 Mon May 12 21:00:23 2003
+++ llvm/lib/Reoptimizer/Inst/lib/Phases.cpp Tue May 13 12:29:49 2003
@@ -284,9 +284,9 @@
m_pTC(p3info->getTraceCache()),
m_pIM(p3info->getIM())
{
- DEBUG_MSG(1, "================ Begin Phase 3 [" << std::hex
- << m_pPhase3Info->getRange().first << ", "
- << m_pPhase3Info->getRange().second
+ DEBUG_MSG(1, "================ Begin Phase 3 ["
+ << HEX(m_pPhase3Info->getRange().first) << ", "
+ << HEX(m_pPhase3Info->getRange().second)
<< "] ================\n");
// 1. Replace the original (replaced) instruction at the proper location in the
@@ -424,7 +424,7 @@
#if VERBOSE > 0
dumpGBT(cerr);
#endif
- DEBUG_MSG(1, "tag is " << m_tag << ", and ");
+ DEBUG_MSG(1, "tag is " << HEX(m_tag) << ", and ");
if(GBTElem* gbte = searchGBT(m_tag)) {
DEBUG_MSG(1, "matches.\n");
@@ -493,28 +493,32 @@
//////////////// Phase 5 implementation ////////////////
-void phase5(GBTElem* gbte, void* paramMem, void* startParamMem)
+void phase5(GBTElem* gbte)
{
DEBUG_MSG(1, "phase5 function invoked\n");
- DEBUG_MSG(1, "gbte->gbtType == " << gbte->gbtType << endl);
- DEBUG_MSG(1, "gbte->paramSize == " << gbte->paramSize << endl);
- DEBUG_MSG(1, "gbte->loadVar (tag) == " << gbte->loadVar << endl);
DEBUG_MSG(1, "Calling instrumentation function...\n");
switch(gbte->gbtType){
case pp::GBT_INTERVAL_START: {
- DEBUG_MSG(1, "paramMem address is " << paramMem << endl);
- DEBUG_MSG(1, "sp+BIAS+off is " << startParamMem << endl);
+ DEBUG_MSG(1, "--- phase 5 start site invocation ---\n");
+ DEBUG_MSG(1, "paramMem address is " << HEX(gbte->paramMem) << endl);
+
void (*instFunc)(void*) = (void (*)(void*)) gbte->instFunc;
- instFunc(paramMem);
+ instFunc(gbte->paramMem);
break;
}
case pp::GBT_INTERVAL_END: {
- DEBUG_MSG(1, "paramMem address is " << paramMem << endl);
- DEBUG_MSG(1, "sp + BIAS + off address is " << startParamMem << endl);
- //DEBUG_MSG(1, "startParamMem address is " << startParamMem << endl);
- //void (*instFunc)(void*, void*) = (void (*)(void*, void*)) gbte->instFunc;
- //instFunc(paramMem, startParamMem);
+ DEBUG_MSG(1, "--- phase 5 start site invocation ---\n");
+ DEBUG_MSG(1, "start parameter is at gbt index " << gbte->gbtStartIdx << endl);
+ DEBUG_MSG(1, "start parameter addr is "
+ << HEX(ppGBT[gbte->gbtStartIdx].paramMem) << endl);
+
+ double tmphack;
+
+ void (*instFunc)(void*, void*) = (void (*)(void*, void*)) gbte->instFunc;
+ instFunc((void*) &tmphack, ppGBT[gbte->gbtStartIdx].paramMem);
+
+ DEBUG_MSG(1, "called end inst func, retval is " << tmphack << endl);
break;
}
}
Index: llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp
diff -u llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.7 llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.8
--- llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.7 Mon May 12 21:00:23 2003
+++ llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp Tue May 13 12:29:50 2003
@@ -77,7 +77,7 @@
void phase3(Phase3Info* p3info);
void phase4(uint64_t tag, Phase4Info* p4info);
-void phase5(GBTElem* gbte, void* paramMem, void* startParamMem);
+void phase5(GBTElem* gbte);
SparcInstManip::SparcInstManip(TraceCache* tc):
InstManip(tc, SHARED_SIZE, INST_WIDTH, NOP_INST),
@@ -230,20 +230,14 @@
(void) p4;
- return GEN_ALLOCA_SIZE +
+ return GEN_SPSUB_SIZE +
GEN_STKSTORE_SIZE +
GEN_STKSTORE_SIZE +
- GEN_SPL_STK_SIZE +
+ GEN_SPL_STK_SIZE +
GEN_LOAD_SIZE +
GEN_STKSTORE_SIZE +
- GEN_SPOFFSET_SIZE +
- GEN_STKSTORE_SIZE +
- // FIXME
- //(type == pp::GBT_INTERVAL_END) ?
- // GEN_SPOFFSET_SIZE + GEN_STKSTORE_SIZE : 0) +
GEN_CALL_SIZE +
- GEN_STKSTORE_SIZE +
- GEN_UNSPL_STK_SIZE +
+ GEN_UNSPL_STK_SIZE +
GEN_STKLOAD_SIZE +
GEN_STKLOAD_SIZE +
GEN_BRANCH_ALWAYS_SIZE;
@@ -284,8 +278,8 @@
for(; start <= end; ++start) {
cout << start << " | "
- << std::hex << std::setw(8) << std::setfill('0')
- << *start << " | ";
+ << std::setw(8) << std::setfill('0')
+ << HEX(*start) << " | ";
sparc_print(*start);
cout << endl;
}
@@ -309,18 +303,23 @@
"Unexpected number of instructions in code sequence for SP load");
}
-// generateAlloca - Generate code to allocate 'size' bytes on the stack
+static unsigned getSPSub(unsigned size)
+{
+ return MK_ADD_R_I(R_O6, R_O6, -size);
+}
+
+// generateSPSub - Generate code to allocate 'size' bytes on the stack
-void SparcInstManip::generateAlloca(unsigned size)
+void SparcInstManip::generateSPSub(unsigned size)
{
assert(m_pCurrSnippet && "Invalid snippet for code generation");
assert(size % STACK_ALIGN == 0 && "SP size is not aligned");
unsigned initSize = m_pCurrSnippet->size();
- m_pCurrSnippet->push_back(MK_ADD_R_I(R_O6, R_O6, -size));
+ m_pCurrSnippet->push_back(getSPSub(size));
- assert(m_pCurrSnippet->size() - initSize == GEN_ALLOCA_SIZE &&
+ assert(m_pCurrSnippet->size() - initSize == GEN_SPSUB_SIZE &&
"Unexpected number of instructions in code sequence for SP add");
}
@@ -892,70 +891,54 @@
const std::pair<uint64_t, uint64_t>& extents,
std::vector<unsigned>& snippet)
{
- // Before we generate code to spill the shared registers, we must first search in the
- // vicinity of the instrumentation site (i.e., the branch to the slot, formerly the
- // load-volatile) to discover a marker alloca that will tell us the correct offset in
- // the current stack frame. The search boundaries are given by the 'extents' pair,
- // which is the address range of the enclosing function.
-
- unsigned offset = findAllocaOffset(instAddr, extents);
unsigned sharedSize = WORD_WIDTH * getSharedSize();
- unsigned stkSize = sharedSize + WORD_WIDTH * 2 + gbte->paramSize;
+ unsigned stkSize = STKFRM_MIN + sharedSize + WORD_WIDTH * 2;
- if(stkSize % STACK_ALIGN != 0)
- cerr << "Warning: not multiple of " << STACK_ALIGN << endl;
+ if(stkSize % STACK_ALIGN != 0) {
+ // Pad up to next multiple of STACK_ALIGN; assumes STACK_ALIGN = 2 * WORD_WIDTH
+ stkSize += WORD_WIDTH;
+ assert(stkSize % STACK_ALIGN == 0 && "Alignment adjustment failed");
+ }
+
+ DEBUG_MSG(1, "buildStartSlot stack offset is " << stkSize << endl);
- DEBUG_MSG(1, "buildStartSlot obtained offset " << std::dec
- << offset << ", and stack size is " << stkSize << std::hex << endl);
+ // Heap-allocate enough memory for the return value of the instrumentation function.
+ assert(!gbte->paramMem && "Expected null paramMem value");
+ gbte->paramMem = static_cast<void*>(new char[gbte->paramSize]);
// After the alloca, our stack region looks like:
- // sp + BIAS + stkSize -> +--------------------------------+
- // | inst function parameter memory | } gbte->paramSize
- // +--------------------------------+
- // | save area for clobbered regs | } WORD_WIDTH * 2
- // +--------------------------------+
- // | spill region for shared regs | } sharedSize
- // sp + BIAS + offset -> +--------------------------------+
-
- // TODO: ensure that stack size is aligned properly
+ // sp + BIAS + stkSize -> +--------------------------------+
+ // | alignment padding |
+ // +--------------------------------+
+ // | save area for clobbered regs | } WORD_WIDTH * 2
+ // +--------------------------------+
+ // | spill region for shared regs | } sharedSize
+ // sp + BIAS + STKFRM_MIN -> +--------------------------------+
+ //
startCode(snippet);
- generateAlloca(stkSize);
+ generateSPSub(stkSize);
// "Manually" save REG_0, REG_1
- generateStackStore(REG_0, offset + sharedSize);
- generateStackStore(REG_1, offset + sharedSize + WORD_WIDTH);
+ generateStackStore(REG_0, STKFRM_MIN + sharedSize);
+ generateStackStore(REG_1, STKFRM_MIN + sharedSize + WORD_WIDTH);
- generateSpillShared(offset);
-
- generateLoad((uint64_t) gbte, REG_0, REG_1); // REG_0 live to call
- generateStackStore(REG_0, PARAM_0);
+ generateSpillShared(STKFRM_MIN);
- DEBUG_MSG(1, "param1 (from offset+bias) = " << std::dec
- << (stkSize - gbte->paramSize)
- << std::hex << endl);
-
- generateSPOffset(REG_1, offset + stkSize - gbte->paramSize); // REG_1 live to call
- generateStackStore(REG_1, PARAM_1);
-
- //tmp -- store %sp + BIAS + offset in third parameter
- generateSPOffset(REG_2, offset);
- generateStackStore(REG_1, PARAM_2);
- //tmp
+ generateLoad((uint64_t) gbte, REG_0, REG_1); // REG_0 live to call
+ generateStackStore(REG_0, PARAM_0);
generateCall((uint64_t) &phase5, slotBase);
- generateRestoreShared(offset);
+ generateRestoreShared(STKFRM_MIN);
// "Manually" restore REG_0, REG_1
- generateStackLoad(REG_0, offset + sharedSize);
- generateStackLoad(REG_1, offset + sharedSize + WORD_WIDTH);
+ generateStackLoad(REG_0, STKFRM_MIN + sharedSize);
+ generateStackLoad(REG_1, STKFRM_MIN + sharedSize + WORD_WIDTH);
- // We need to branch back to one instruction beyond the branch to the phase 5 slot.
- generateBranchAlways(instAddr + getInstWidth(), slotBase, getNOP());
- endCode();
+ generateBranchAlways(instAddr + getInstWidth(), slotBase, getSPSub(-stkSize));
- // TODO: Add assert against against the snippet size.
+ endCode();
}
void SparcInstManip::buildEndIntervalSlot(GBTElem* gbte,
@@ -964,84 +947,36 @@
const std::pair<uint64_t, uint64_t>& extents,
std::vector<unsigned>& snippet)
{
- unsigned offset = findAllocaOffset(instAddr, extents);
unsigned sharedSize = WORD_WIDTH * getSharedSize();
- unsigned stkSize = sharedSize + WORD_WIDTH * 2 + gbte->paramSize;
-
- if(stkSize % STACK_ALIGN != 0)
- cerr << "Warning: not multiple of STACK_ALIGN" << endl;
-
- DEBUG_MSG(1, "buildEndSlot obtained offset " << std::dec
- << offset << ", and stack size is " << stkSize << std::hex << endl);
-
- // After the alloca, our stack region looks like:
- // (current implementation assumes no %sp manipulation occurs between start- and
- // end-region sites)
- // +--------------------------------+
- // | ... stk area for start site ...|
- // sp + BIAS + stkSize -> +--------------------------------+
- // | inst function param1 memory | } gbte->paramSize
- // +--------------------------------+
- // | save area for clobbered regs | } WORD_WIDTH * 2
- // +--------------------------------+
- // | spill region for shared regs | } sharedSize
- // sp + BIAS + offset -> +--------------------------------+
- //
+ unsigned stkSize = STKFRM_MIN + sharedSize + WORD_WIDTH * 2;
- // TODO: ensure that stack size is aligned properly
+ if(stkSize % STACK_ALIGN != 0) {
+ // Pad up to next multiple of STACK_ALIGN; assumes STACK_ALIGN = 2 * WORD_WIDTH
+ stkSize += WORD_WIDTH;
+ assert(stkSize % STACK_ALIGN == 0 && "Alignment adjustment failed");
+ }
+ DEBUG_MSG(1, "buildEndSlot stack offset is " << stkSize << endl);
+
startCode(snippet);
-
- generateAlloca(stkSize);
-
+ generateSPSub(stkSize);
+
// "Manually" save REG_0, REG_1
- generateStackStore(REG_0, offset + sharedSize);
- generateStackStore(REG_1, offset + sharedSize + WORD_WIDTH);
-
- generateSpillShared(offset);
-
+ generateStackStore(REG_0, STKFRM_MIN + sharedSize);
+ generateStackStore(REG_1, STKFRM_MIN + sharedSize + WORD_WIDTH);
+
+ generateSpillShared(STKFRM_MIN);
generateLoad((uint64_t) gbte, REG_0, REG_1); // REG_0 live to call
generateStackStore(REG_0, PARAM_0);
-
- DEBUG_MSG(1, "param1 (from offset+bias) = " << std::dec
- << (stkSize - gbte->paramSize)
- << std::hex << endl);
-
- generateSPOffset(REG_1, offset + stkSize - gbte->paramSize); // REG_1 live to call
- generateStackStore(REG_1, PARAM_1);
-
- // Generate code for computing the address of stack location where the return value of
- // the start site is kept (i.e., -paramSize from the top of the start-region stack
- // region). Note that we have made the KIS concession that no %sp manipulation may
- // occur in between start- and end-region sites, and that the size of the return
- // values for the start and end instrumentation functions are equal.
-
- DEBUG_MSG(1, "param2 (from offset+bias) = " << std::dec
- << (2 * stkSize - gbte->paramSize)
- << std::hex << endl);
-
-#if 0
- generateSPOffset(REG_2, offset + 2 * stkSize - gbte->paramSize);
- generateStackStore(REG_2, PARAM_2);
-#endif
-
- //tmp -- store %sp + BIAS + offset in third parameter
- generateSPOffset(REG_2, offset);
- generateStackStore(REG_1, PARAM_2);
- //tmp
-
generateCall((uint64_t) &phase5, slotBase);
- generateRestoreShared(offset);
-
+ generateRestoreShared(STKFRM_MIN);
+
// "Manually" restore REG_0, REG_1
- generateStackLoad(REG_0, offset + sharedSize);
- generateStackLoad(REG_1, offset + sharedSize + WORD_WIDTH);
-
- // We need to branch back to one instruction beyond the branch to the phase 5 slot.
- generateBranchAlways(instAddr + getInstWidth(), slotBase, getNOP());
- endCode();
+ generateStackLoad(REG_0, STKFRM_MIN + sharedSize);
+ generateStackLoad(REG_1, STKFRM_MIN + sharedSize + WORD_WIDTH);
+ generateBranchAlways(instAddr + getInstWidth(), slotBase, getSPSub(-stkSize));
- // TODO: Add assert against against the snippet size.
+ endCode();
}
Index: llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h
diff -u llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.8 llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.9
--- llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.8 Mon May 12 21:00:23 2003
+++ llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h Tue May 13 12:29:50 2003
@@ -64,7 +64,7 @@
void generateCall(uint64_t dest, uint64_t slotBase);
void generateSPOffset(LogicalRegister reg, unsigned offset);
- void generateAlloca(unsigned size);
+ void generateSPSub(unsigned size);
void generateLoad(uint64_t value,
LogicalRegister dest,
@@ -150,6 +150,7 @@
static const unsigned INST_WIDTH = 4; // In bytes
static const unsigned NOP_INST = 0x01000000;
static const unsigned BIAS = 2047;
+ static const unsigned STKFRM_MIN = 176; // Smallest allowable stack frm size
static const unsigned STACK_ALIGN = 16;
static const unsigned SEARCH_DELTA = 20;
static const unsigned WORD_WIDTH = 8;
@@ -169,7 +170,7 @@
static const unsigned GEN_SPL_STK_SIZE = SHARED_SIZE;
static const unsigned GEN_UNSPL_SIZE = GEN_SPL_SIZE;
static const unsigned GEN_UNSPL_STK_SIZE = GEN_SPL_STK_SIZE;
- static const unsigned GEN_ALLOCA_SIZE = 1;
+ static const unsigned GEN_SPSUB_SIZE = 1;
static const unsigned GEN_SPOFFSET_SIZE = 1;
};
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