[llvm-commits] CVS: llvm/lib/Reoptimizer/Inst/lib/InstManip.h PhaseInfo.h Phases.cpp SparcInstManip.cpp SparcInstManip.h
Joel Stanley
jstanley at cs.uiuc.edu
Thu May 8 12:18:02 PDT 2003
Changes in directory llvm/lib/Reoptimizer/Inst/lib:
InstManip.h updated: 1.15 -> 1.16
PhaseInfo.h updated: 1.2 -> 1.3
Phases.cpp updated: 1.24 -> 1.25
SparcInstManip.cpp updated: 1.4 -> 1.5
SparcInstManip.h updated: 1.5 -> 1.6
---
Log message:
Phase 5 slot functioning, and alloca markers are being discovered correctly. DEBUG macros
added to clean up the code a bit. Changed SparcInstManip to use class constants over
functions that ended up never becoming virtual as originally intended.
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/Inst/lib/InstManip.h
diff -u llvm/lib/Reoptimizer/Inst/lib/InstManip.h:1.15 llvm/lib/Reoptimizer/Inst/lib/InstManip.h:1.16
--- llvm/lib/Reoptimizer/Inst/lib/InstManip.h:1.15 Wed May 7 20:50:06 2003
+++ llvm/lib/Reoptimizer/Inst/lib/InstManip.h Thu May 8 11:27:25 2003
@@ -72,7 +72,7 @@
virtual void buildSlot(PrimInfo* pi,
uint64_t slotBase,
uint64_t instAddr,
- uint64_t startAddr,
+ const std::pair<uint64_t, uint64_t>& extents,
std::vector<unsigned>& snippet) = 0;
virtual unsigned getSlotSize(Phase2* p2) const = 0;
@@ -83,8 +83,7 @@
// region defined by the given addresses. This is necessarily a platform-dependent
// action.
- virtual void findCandidates(uint64_t start,
- uint64_t end,
+ virtual void findCandidates(const std::pair<uint64_t, uint64_t>& range,
std::vector<InstCandidate>& candidates) = 0;
// getStartAddr - return the desired starting position in the function body. This is
Index: llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h
diff -u llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h:1.2 llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h:1.3
--- llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h:1.2 Wed May 7 20:50:06 2003
+++ llvm/lib/Reoptimizer/Inst/lib/PhaseInfo.h Thu May 8 11:27:25 2003
@@ -13,6 +13,13 @@
class TraceCache;
class InstManip;
+#define DEBUG 1
+#if DEBUG
+#define DEBUG_MSG(x) std::cerr << x
+#else
+#define DEBUG_MSG(x)
+#endif
+
typedef std::pair<uint64_t, uint64_t> AddressRange;
typedef struct PrimInfo {
@@ -24,14 +31,14 @@
class Phase3Info
{
public:
- Phase3Info(const AddressRange& addressRange,
+ Phase3Info(const AddressRange& range,
unsigned origInst,
uint64_t replaceAddr,
uint64_t slotDescriptor,
unsigned slotSize,
TraceCache* pTC,
InstManip* pIM):
- m_addrRange(addressRange),
+ m_range(range),
m_origInst(origInst),
m_replaceAddr(replaceAddr),
m_slotDescriptor(slotDescriptor),
@@ -44,26 +51,25 @@
void print(std::ostream& ostr)
{
ostr << std::hex << "Phase3Info instance: {" << std::endl
- << " Function address range: [" << m_addrRange.first << ", "
- << m_addrRange.second << "]" << std::endl
+ << " Function address range: [" << m_range.first << ", "
+ << m_range.second << "]" << std::endl
<< " To replace: [" << m_origInst << " @ "
<< m_replaceAddr << "]" << std::endl
<< "}" << std::endl;
}
- uint64_t getStartAddr() const { return m_addrRange.first; }
- uint64_t getEndAddr() const { return m_addrRange.second; }
- uint64_t getOrigInst() const { return m_origInst; }
- uint64_t getReplaceAddr() const { return m_replaceAddr; }
- uint64_t getSlot() const { return m_slotDescriptor; }
- uint64_t getSlotSize() const { return m_slotSize; }
- TraceCache* getTraceCache() { return m_pTC; }
- InstManip* getIM() { return m_pIM; }
+ const AddressRange& getRange() const { return m_range; }
+ uint64_t getOrigInst() const { return m_origInst; }
+ uint64_t getReplaceAddr() const { return m_replaceAddr; }
+ uint64_t getSlot() const { return m_slotDescriptor; }
+ uint64_t getSlotSize() const { return m_slotSize; }
+ TraceCache* getTraceCache() { return m_pTC; }
+ InstManip* getIM() { return m_pIM; }
private:
Phase3Info() {}
- AddressRange m_addrRange; // Range of function for phase 3 to examine
+ AddressRange m_range; // Range of function for phase 3 to examine
unsigned m_origInst; // Instruction replaced by phase 2
uint64_t m_replaceAddr; // Address at which to restore original inst
uint64_t m_slotDescriptor; // Slot created by phase 2
@@ -76,13 +82,13 @@
{
public:
Phase4Info(const InstCandidate& candidate,
- uint64_t startAddr,
+ const AddressRange& range,
uint64_t slotDescriptor,
uint64_t slotSize,
TraceCache* pTC,
InstManip* pIM):
m_candidate(candidate),
- m_startAddr(startAddr),
+ m_range(range),
m_slotDescriptor(slotDescriptor),
m_slotSize(slotSize),
m_pTC(pTC),
@@ -90,18 +96,18 @@
{
}
- const InstCandidate& getCandidate() const { return m_candidate; }
- uint64_t getStartAddr() const { return m_startAddr; }
- uint64_t getSlot() const { return m_slotDescriptor; }
- uint64_t getSlotSize() const { return m_slotSize; }
- TraceCache* getTraceCache() { return m_pTC; }
- InstManip* getIM() { return m_pIM; }
+ const InstCandidate& getCandidate() const { return m_candidate; }
+ const AddressRange& getRange() const { return m_range; }
+ uint64_t getSlot() const { return m_slotDescriptor; }
+ uint64_t getSlotSize() const { return m_slotSize; }
+ TraceCache* getTraceCache() { return m_pTC; }
+ InstManip* getIM() { return m_pIM; }
private:
Phase4Info() {}
InstCandidate m_candidate; // Candidate responsible for this instance's creation
- uint64_t m_startAddr; // Start address of enclosing function
+ AddressRange m_range; // Start address of enclosing function
uint64_t m_slotDescriptor; // Slot created by phase 3
unsigned m_slotSize; // Size of slot created by phase 3
TraceCache* m_pTC; // TraceCache instance used by phases 2 and 3
Index: llvm/lib/Reoptimizer/Inst/lib/Phases.cpp
diff -u llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.24 llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.25
--- llvm/lib/Reoptimizer/Inst/lib/Phases.cpp:1.24 Wed May 7 20:50:06 2003
+++ llvm/lib/Reoptimizer/Inst/lib/Phases.cpp Thu May 8 11:27:25 2003
@@ -66,14 +66,6 @@
#include "PhaseInfo.h"
#include "SparcInstManip.h"
-#define DEBUG 1
-
-#if DEBUG
-#define DEBUG_MSG(x) std::cerr << x << std::endl
-#else
-#define DEBUG_MSG(x)
-#endif
-
using std::vector;
using std::cerr;
using std::endl;
@@ -169,10 +161,10 @@
void Phase2::transform()
{
- DEBUG_MSG("============================== Begin Phase 2 ==============================");
+ DEBUG_MSG("============================== Begin Phase 2 ==============================\n");
const char* execName = getexecname();
- DEBUG_MSG("Executable name is: " << execName);
+ DEBUG_MSG("Executable name is: " << execName << endl);
ElfReader elfReader(execName);
@@ -199,13 +191,13 @@
//cerr << i->first << " is to be transformed" << endl;
if(i->first == "fibs") {
- DEBUG_MSG("Transforming function " << i->first << "...");
+ DEBUG_MSG("Transforming function " << i->first << "...\n");
transformFunction(i->second);
}
}
}
- DEBUG_MSG("============================== End Phase 2 ===========================");
+ DEBUG_MSG("============================== End Phase 2 ===========================\n");
}
@@ -271,7 +263,7 @@
m_pIM->buildSlot(p3info, snippet);
#if DEBUG
- DEBUG_MSG("phase3 slot instructions:");
+ DEBUG_MSG("phase3 slot instructions:\n");
dumpSnippet(snippet, m_pIM);
#endif
@@ -293,8 +285,9 @@
m_pIM(p3info->getIM())
{
DEBUG_MSG("================ Begin Phase 3 [" << std::hex
- << m_pPhase3Info->getStartAddr() << ", " << m_pPhase3Info->getEndAddr()
- << "] ================");
+ << m_pPhase3Info->getRange().first << ", "
+ << m_pPhase3Info->getRange().second
+ << "] ================\n");
// 1. Replace the original (replaced) instruction at the proper location in the
// original code (thus effectively removing the branch to the slot created by phase 2
@@ -326,10 +319,10 @@
// For each load candidate, obtain a new slot and write the phase 4 slot region
// contents into it.
- DEBUG_MSG("There are " << candidates.size() << " candidates to process");
+ DEBUG_MSG("There are " << candidates.size() << " candidates to process\n");
for(vector<InstCandidate>::iterator i = candidates.begin(), e = candidates.end(); i != e; ++i) {
- DEBUG_MSG("Transforming " << *i);
+ DEBUG_MSG("Transforming " << *i << endl);
unsigned slotSize = m_pIM->getSlotSize(this, *i);
// Replace load candidate instruction with a branch to the start of a new slot.
@@ -338,14 +331,14 @@
// Build the Phase4Info structure and generate the phase 4 slot.
- Phase4Info* p4info = new Phase4Info(*i, m_pPhase3Info->getStartAddr(),
+ Phase4Info* p4info = new Phase4Info(*i, m_pPhase3Info->getRange(),
slotBase, slotSize, m_pTC, m_pIM);
vector<unsigned> snippet;
m_pIM->buildSlot(p4info, snippet);
#if DEBUG
- DEBUG_MSG("phase4 slot instructions:");
+ DEBUG_MSG("phase4 slot instructions:\n");
dumpSnippet(snippet, m_pIM);
#endif
@@ -361,13 +354,11 @@
{
// 2. Analyze the function and determine the load-volatile candidates...
vector<InstCandidate> candidates;
- m_pIM->findCandidates(m_pPhase3Info->getStartAddr(),
- m_pPhase3Info->getEndAddr(),
- candidates);
+ m_pIM->findCandidates(m_pPhase3Info->getRange(), candidates);
// ...and process them
processCandidates(candidates);
- DEBUG_MSG("============================== End Phase 3 ==============================");
+ DEBUG_MSG("============================== End Phase 3 ==============================\n");
}
//////////////// Phase4 implementation ////////////////
@@ -384,7 +375,7 @@
m_pIM(p4info->getIM()),
m_tag(tag)
{
- DEBUG_MSG("================ Begin Phase 4 ================");
+ DEBUG_MSG("================ Begin Phase 4 ================\n");
}
Phase4::~Phase4()
@@ -431,12 +422,12 @@
{
#if DEBUG
- DEBUG_MSG("tag is " << m_tag);
- dumpGBT(cerr);
+ //dumpGBT(cerr);
+ DEBUG_MSG("tag is " << m_tag << ", and ");
#endif
if(PrimInfo* pi = searchGBT(m_tag)) {
- DEBUG_MSG("Tag matches.");
+ DEBUG_MSG("matches.\n");
const InstCandidate& cand = m_pPhase4Info->getCandidate();
assert(cand.getInsts().size() >= 2
@@ -458,10 +449,10 @@
uint64_t slotBase = replaceInstWithBrToSlot(repAddr, slotSize, m_pTC, m_pIM);
vector<unsigned> snippet;
- m_pIM->buildSlot(pi, slotBase, repAddr, m_pPhase4Info->getStartAddr(), snippet);
+ m_pIM->buildSlot(pi, slotBase, repAddr, m_pPhase4Info->getRange(), snippet);
#if DEBUG
- DEBUG_MSG("phase 5 slot contents: ");
+ DEBUG_MSG("phase 5 slot contents:\n");
dumpSnippet(snippet, m_pIM);
#endif
@@ -479,7 +470,7 @@
#endif
}
else {
- DEBUG_MSG("Could not find tag");
+ DEBUG_MSG("does not match\n");
// The candidate failed to get elected, so pack up and go home. Restore the
// replaced instruction (i.e. the branch that invoked this code) with the original
// instruction at that location.
@@ -497,12 +488,12 @@
m_pPhase4Info->getCandidate().front().second);
#endif
- DEBUG_MSG("================ End Phase 4 ================");
+ DEBUG_MSG("================ End Phase 4 ================\n");
}
//////////////// Phase 5 implementation ////////////////
void phase5(PrimInfo* pi)
{
- DEBUG_MSG("phase5 function invoked");
+ DEBUG_MSG("phase5 function invoked\n");
}
Index: llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp
diff -u llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.4 llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.5
--- llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp:1.4 Wed May 7 20:50:06 2003
+++ llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.cpp Thu May 8 11:27:25 2003
@@ -33,6 +33,24 @@
// | branch back to orig code |
// | restore registers |
// +---------------------------------------+
+//
+// Phase 5 slot:
+// NB: Slot does *not* save registers with the 'save' instruction, because
+// it must perform the alloca within the stack frame of the code that
+// invoked it.
+// +-------------------------------------------+
+// | manually-save clobbered registers |
+// | alloc spill area & inst param on stack |
+// | spill shared registers |
+// | copy PrimInfo ptr to param 1 |
+// | copy spill area addr to param 2 |
+// | call phase 5 |
+// | nop |
+// | restore shared registers |
+// | manually-restore clobbered registers |
+// | branch back to orig code |
+// | nop |
+// +-------------------------------------------+
// []
#include <iostream>
@@ -153,17 +171,18 @@
void SparcInstManip::buildSlot(PrimInfo* pi,
uint64_t slotBase,
uint64_t instAddr,
- uint64_t startAddr,
+ const std::pair<uint64_t, uint64_t>& extents,
std::vector<unsigned>& snippet)
{
- // Before we generate code to spill the shared registers, we must first search
- // backwards from the instrumentation site (i.e., the branch to the slot, formerly the
+ // Before we generate code to spill the shared registers, we must first search in the
+ // vicinity of the instrumentation site (i.e., the branch to the slot, formerly the
// load-volatile) to discover a marker alloca that will tell us the correct offset in
- // the current stack frame. startAddr is the starting address of the function
- // containing the instrumentation site. We will search backwards from instAddr for a
- // valid alloca marker, stopping at startAddr if we do not encounter one.
+ // the current stack frame. The search boundaries are given by the 'extents' pair,
+ // which is the address range of the enclosing function.
- unsigned offset = findAllocaOffset(instAddr, startAddr);
+ unsigned offset = findAllocaOffset(instAddr, extents);
+ DEBUG_MSG("buildSlot(p5) obtained offset " << std::dec
+ << offset << std::hex << endl);
startCode(snippet);
@@ -225,13 +244,13 @@
return GEN_SAVE_SIZE + GEN_CALL_SIZE + GEN_BRANCH_ALWAYS_SIZE;
}
-void SparcInstManip::findCandidates(uint64_t start,
- uint64_t end,
+void SparcInstManip::findCandidates(const std::pair<uint64_t, uint64_t>& range,
vector<InstCandidate>& candidates)
{
- for(uint64_t currAddr = start; currAddr <= end; currAddr += getInstWidth()) {
+ for(uint64_t currAddr = range.first;
+ currAddr <= range.second; currAddr += getInstWidth()) {
InstCandidate cand(this);
- if(isCandidateLoad(currAddr, end, cand))
+ if(isCandidateLoad(currAddr, range.second, cand))
candidates.push_back(cand);
}
}
@@ -249,7 +268,7 @@
}
void SparcInstManip::printRange(unsigned* start,
- unsigned* end) const
+ unsigned* end) const
{
// Dumps contents (and corresponding disassembly) of memory range given by range
// to stdout. TODO: Parameterize by an ostream instance; cannot do this yet
@@ -348,7 +367,7 @@
}
void SparcInstManip::generateParamStore(LogicalRegister src,
- StackOffset off)
+ StackOffset off)
{
assert(m_pCurrSnippet && "Invalid snippet for code generation");
vector<unsigned>& snippet = *m_pCurrSnippet;
@@ -363,7 +382,7 @@
}
void SparcInstManip::generateCall(uint64_t dest,
- uint64_t slotBase)
+ uint64_t slotBase)
{
assert(m_pCurrSnippet && "Invalid snippet for code generation");
vector<unsigned>& snippet = *m_pCurrSnippet;
@@ -540,9 +559,9 @@
}
bool SparcInstManip::determineSchema(InstCandidate& cand,
- uint64_t end,
- std::pair<uint64_t, unsigned>& load,
- std::pair<uint64_t, unsigned>& store)
+ uint64_t end,
+ std::pair<uint64_t, unsigned>& load,
+ std::pair<uint64_t, unsigned>& store)
{
// inst1 contains the load instruction (the actual candidate). inst2 contains the
// corresponding store instruction, which is either STB or STH. If STB, take actions
@@ -597,8 +616,8 @@
}
bool SparcInstManip::isCandidateLoad(uint64_t addr,
- uint64_t end,
- InstCandidate& cand)
+ uint64_t end,
+ InstCandidate& cand)
{
// {{{ Description of heuristic
@@ -656,8 +675,8 @@
}
uint64_t SparcInstManip::findNextStackLoad(uint64_t addr,
- uint64_t end,
- unsigned fpOffset)
+ uint64_t end,
+ unsigned fpOffset)
{
// Sweep the range of addresses starting at addr, up to end, looking for a load byte
// that is loading from [%fp + fpOffset]. Return the first such instance, or 0 is such
@@ -674,8 +693,8 @@
}
uint64_t SparcInstManip::findNextStore(uint64_t addr,
- uint64_t end,
- unsigned srcReg)
+ uint64_t end,
+ unsigned srcReg)
{
// Sweep the range of addresses starting at addr, up to end, looking for stb or sth
// instructions that are storing _from_ 'fromReg'. Return the first such instance, or
@@ -690,7 +709,83 @@
return 0;
}
-unsigned SparcInstManip::findAllocaOffset(uint64_t instAddr, uint64_t startAddr)
+bool SparcInstManip::isAllocaSignature(unsigned inst, unsigned& offset)
{
+ if(RD_FLD(inst, INSTR_OP) == OP_2 &&
+ RD_FLD(inst, INSTR_OP3) == OP3_ADD &&
+ RD_FLD(inst, INSTR_I) == 1 &&
+ RD_FLD(inst, INSTR_RS1) == R_O6 && // Src == %sp
+ RD_FLD(inst, INSTR_RD) != R_O6) { // Target != %sp
+
+ // Examine the immediate value and determine if it falls into one of the two
+ // special cases, with an as-yet-unimplemented fallback (TODO). Stack addresses
+ // must be multiples of STACK_ALIGN (16 for SparcV9). We also know that the alloca
+ // we are concerned about is always of size STACK_ALIGN (the minimum size). The
+ // compiler generates an a value v = (immediate value - BIAS) such that
+ //
+ // a) v is a multiple of STACK_ALIGN -or-
+ // b) v - STACK_ALIGN + 1 is a multiple of STACK_ALIGN
+ //
+ // This is gross and hackish but it'll do for the time being.
+
+ unsigned imm = RD_FLD(inst, INSTR_SIMM13);
+
+ if(0 == (imm - BIAS) % STACK_ALIGN) {
+ offset = imm - BIAS;
+ DEBUG_MSG("Alloca marker case (a)\n");
+ }
+ else if(0 == (imm - BIAS - STACK_ALIGN + 1) % STACK_ALIGN) {
+ offset = imm - BIAS - STACK_ALIGN + 1;
+ DEBUG_MSG("Alloca marker case (b)\n");
+ }
+ else
+ assert(0 && "Alloca special cases failed, need fallback implementation");
+
+#if DEBUG
+ DEBUG_MSG("Found alloca marker: ");
+ sparc_print(inst);
+ fflush(stdout);
+ DEBUG_MSG(endl);
+#endif
+ return true;
+ }
+
+ return false;
+}
+
+unsigned SparcInstManip::findAllocaOffset(uint64_t instAddr,
+ const std::pair<uint64_t, uint64_t>& range)
+{
+ // Search around the vicinity of instAddr, looking for the alloca instance (more
+ // specifically, the "second" part of the alloca -- the add of the "magic" offset to
+ // the stack pointer with a non-SP destination reg) that *must* exist if Phase 1
+ // worked properly (introduced an immutable alloca). Unfortunately, we cannot
+ // guarantee instruction ordering, so we have to search both forwards and backwards,
+ // within the bounds of the function.
+
+ uint64_t curr;
+
+ // Search backwards from SEARCH_DELTA instructions beyond the instrumentation site (or
+ // the end of the function, whichever is closer). We start ahead by SEARCH_DELTA to
+ // catch the common case where the instruction we are looking for occurs very soon
+ // after the instrumentation site.
+
+ curr = std::min<uint64_t>(instAddr + SEARCH_DELTA * getInstWidth(), range.second);
+ for( ; curr >= range.first; curr -= getInstWidth()) {
+ unsigned inst = m_pTC->getVM()->readInstrFrmVm(curr);
+ unsigned offset;
+ if(isAllocaSignature(inst, offset))
+ return offset;
+ }
+
+ // Forwards from instrumentation site to function end
+ for(curr = instAddr + getInstWidth(); curr <= range.second; curr += getInstWidth()) {
+ unsigned inst = m_pTC->getVM()->readInstrFrmVm(curr);
+ unsigned offset;
+ if(isAllocaSignature(inst, offset))
+ return offset;
+ }
+
+ assert(0 && "Failed to find alloca marker");
return 0;
}
Index: llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h
diff -u llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.5 llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.6
--- llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h:1.5 Wed May 7 20:50:06 2003
+++ llvm/lib/Reoptimizer/Inst/lib/SparcInstManip.h Thu May 8 11:27:25 2003
@@ -34,15 +34,14 @@
virtual void buildSlot(PrimInfo* pi,
uint64_t slotBase,
uint64_t instAddr,
- uint64_t startAddr,
+ const std::pair<uint64_t, uint64_t>& extents,
std::vector<unsigned>& snippet);
virtual unsigned getSlotSize(Phase2* p2) const;
virtual unsigned getSlotSize(Phase3* p3, InstCandidate& cand) const;
virtual unsigned getSlotSize(Phase4* p4) const;
- virtual void findCandidates(uint64_t start,
- uint64_t end,
+ virtual void findCandidates(const std::pair<uint64_t, uint64_t>& range,
std::vector<InstCandidate>& candidates);
virtual uint64_t getStartAddr(uint64_t funcStartAddr) const;
@@ -108,7 +107,10 @@
uint64_t end,
unsigned fpOffset);
- unsigned findAllocaOffset(uint64_t instAddr, uint64_t startAddr);
+ unsigned findAllocaOffset(uint64_t instAddr,
+ const std::pair<uint64_t, uint64_t>& range);
+
+ static bool isAllocaSignature(unsigned inst, unsigned& offset);
std::vector<unsigned>* m_pCurrSnippet;
OutputToInputRegMap m_outputToInputReg; // Maps input register -> output register
@@ -130,9 +132,11 @@
// Branch-always (annul bit low) instruction base (address not filled in yet)
static const unsigned BRANCH_ALWAYS_BASE;
- static const unsigned INST_WIDTH = 4; // In bytes
- static const unsigned NOP_INST = 0x01000000;
- static const unsigned BIAS = 2047;
+ static const unsigned INST_WIDTH = 4; // In bytes
+ static const unsigned NOP_INST = 0x01000000;
+ static const unsigned BIAS = 2047;
+ static const unsigned STACK_ALIGN = 16;
+ static const unsigned SEARCH_DELTA = 20;
// Fixed sizes of generated SparcV9 assembly snippets
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