[llvm-commits] CVS: llvm/lib/Reoptimizer/Inst/InstManip.cpp InstManip.h Phase2.cpp design.txt
Joel Stanley
jstanley at cs.uiuc.edu
Thu Apr 10 00:34:00 PDT 2003
Changes in directory llvm/lib/Reoptimizer/Inst:
InstManip.cpp updated: 1.1 -> 1.2
InstManip.h updated: 1.1 -> 1.2
Phase2.cpp updated: 1.4 -> 1.5
design.txt updated: 1.6 -> 1.7
---
Log message:
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/Inst/InstManip.cpp
diff -u llvm/lib/Reoptimizer/Inst/InstManip.cpp:1.1 llvm/lib/Reoptimizer/Inst/InstManip.cpp:1.2
--- llvm/lib/Reoptimizer/Inst/InstManip.cpp:1.1 Tue Apr 8 23:32:03 2003
+++ llvm/lib/Reoptimizer/Inst/InstManip.cpp Thu Apr 10 00:35:02 2003
@@ -38,18 +38,21 @@
return RD_FLD(inst, INSTR_OP3) == OP3_SAVE ? addr + 4 : addr;
}
-void InstManip::generateLoad64(uint64_t value, std::vector<unsigned>& snippet) const
+void InstManip::generateLoad64(uint64_t value,
+ std::vector<unsigned>& snippet,
+ TargetRegister reg) const
{
// Using %o0 and %o1, load the 64-bit value 'value' into %o0. The sequence of
// instructions to do this is placed in the provided instruction vector 'snippet'.
unsigned initSize = snippet.size();
- snippet.push_back(0x11000000 | high22(highWord(value))); // sethi (upper 22b of upper wrd), %o0
- snippet.push_back(0x90122000 | low10(highWord(value))); // or %o0, (lower 10b of upper wrd), %o0
+
+ snippet.push_back(0x11000000 | HIGH22(HIGHWORD(value))); // sethi (upper 22b of upper wrd), %o0
+ snippet.push_back(0x90122000 | LOW10(HIGHWORD(value))); // or %o0, (lower 10b of upper wrd), %o0
snippet.push_back(0x912a3020); // sllx %o0, 32, %o0
- snippet.push_back(0x13000000 | high22(lowWord(value))); // sethi (upper 22b of lwr wrd), %o1
+ snippet.push_back(0x13000000 | HIGH22(LOWWORD(value))); // sethi (upper 22b of lwr wrd), %o1
snippet.push_back(0x90120009); // or %o0, %o1, %o0
- snippet.push_back(0x90022000 | low10(lowWord(value))); // add %o0, (lwr 10b of lwr wrd), %o0
+ snippet.push_back(0x90022000 | LOW10(LOWWORD(value))); // add %o0, (lwr 10b of lwr wrd), %o0
assert(snippet.size() - initSize == getGenLoad64Size() &&
"Unexpected number of instructions in code sequence for 64-bit value -> %o0");
Index: llvm/lib/Reoptimizer/Inst/InstManip.h
diff -u llvm/lib/Reoptimizer/Inst/InstManip.h:1.1 llvm/lib/Reoptimizer/Inst/InstManip.h:1.2
--- llvm/lib/Reoptimizer/Inst/InstManip.h:1.1 Tue Apr 8 23:32:03 2003
+++ llvm/lib/Reoptimizer/Inst/InstManip.h Thu Apr 10 00:35:03 2003
@@ -21,6 +21,8 @@
class InstManip
{
public:
+ enum TargetRegister { REG_0, REG_1 };
+
void printRange(unsigned* start, unsigned* end) const;
inline void printRange(uint64_t start, uint64_t end) const;
@@ -29,7 +31,9 @@
uint64_t skipFunctionHdr(uint64_t addr, VirtualMem* vm) const;
- void generateLoad64(uint64_t value, std::vector<unsigned>& snippet) const;
+ void generateLoad64(uint64_t value,
+ std::vector<unsigned>& snippet,
+ TargetRegister reg = REG_0) const;
inline unsigned getBranchAlways(uint64_t dest, uint64_t pc, bool annulHigh = true) const;
inline unsigned getCall(uint64_t dest, uint64_t pc) const;
@@ -38,18 +42,12 @@
unsigned getNOP() const { return 0x01000000; }
unsigned getGenLoad64Size() const { return 6; }
-
private:
////////////////
// Instruction constants and field-extraction "macros", etc.
// Branch-always (annul bit high) instruction base (i.e. address not filled in yet)
static const unsigned BRANCH_ALWAYS_BASE = 0x30480000;
-
- static unsigned low10(unsigned value) { return value & 0x000003ff; }
- static unsigned high22(unsigned value) { return value >> 10; }
- static unsigned highWord(uint64_t value) { return (unsigned) (value >> 32); }
- static unsigned lowWord(uint64_t value) { return (unsigned) value; }
};
void InstManip::printRange(uint64_t start, uint64_t end) const
Index: llvm/lib/Reoptimizer/Inst/Phase2.cpp
diff -u llvm/lib/Reoptimizer/Inst/Phase2.cpp:1.4 llvm/lib/Reoptimizer/Inst/Phase2.cpp:1.5
--- llvm/lib/Reoptimizer/Inst/Phase2.cpp:1.4 Tue Apr 8 23:32:03 2003
+++ llvm/lib/Reoptimizer/Inst/Phase2.cpp Thu Apr 10 00:35:03 2003
@@ -122,9 +122,7 @@
MemoryManager* mm = m_traceCache.getMemMgr();
uint64_t slotBase = mm->getMemory(getSlotSize());
unsigned origInstr = vm->readInstrFrmVm(repInstAddr);
-
- if(m_instManip.isBranch(origInstr))
- assert(0 && "Unhandled case: branch instruction first in function body");
+ assert(!m_instManip.isBranch(origInstr) && "Unhandled case: branch instruction first in function body");
// Replace the instruction at repInstAddr with a branch to the start of the slot
vm->writeInstToVM(repInstAddr, m_instManip.getBranchAlways(slotBase, repInstAddr));
Index: llvm/lib/Reoptimizer/Inst/design.txt
diff -u llvm/lib/Reoptimizer/Inst/design.txt:1.6 llvm/lib/Reoptimizer/Inst/design.txt:1.7
--- llvm/lib/Reoptimizer/Inst/design.txt:1.6 Fri Apr 4 17:08:56 2003
+++ llvm/lib/Reoptimizer/Inst/design.txt Thu Apr 10 00:35:03 2003
@@ -653,7 +653,7 @@
}}}
-{{{ MEETING MINUTES 03 Apr 3003
+{{{ MEETING MINUTES 03 Apr 2003
New definition of different phases:
@@ -726,6 +726,28 @@
}}}
+{{{ MEETING MINUTES 09 Apr 2003
+
+- Talked about ICS reviewer comments; for thesis work, or for later papers, we must keep
+in mind the following:
+
+ - Related work in the RT field, esp. language support for metrics. How are we
+ different? We need to read the current literature on this.
+
+ - Address in the writing the difference between our approach and standard measurement
+ tools, specifically SpeedShop and other hardware-counter-related tools. I thought we
+ did this, but apparently we weren't very clear.
+
+- Must concentrate on results and finished implementation in the short-term.
+
+- To that end, we discussed using the dummy function memory and how to re-use it. Because
+it's a fixed-size thing, we ought to only place indirect jumps to heap-allocated memory
+there, and then, in the heap-allocated memory write the actual code to do the
+instrumentation, etc, etc.
+
+- Rewrite instruction building mechanisms are general BinInterface macros. Blech.
+
+}}}
{{{ IMPLEMENTATION SKETCH
{{{ Current implementation sketch:
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