[llvm-commits] CVS: llvm/test/Programs/Makefile.programs

[Chris Lattner]

Changes in directory llvm/test/Programs:

Makefile.programs updated: 1.21 -> 1.22

---
Log message:

Implement support for 'make TEST=foo'


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Diffs of the changes:

Index: llvm/test/Programs/Makefile.programs
diff -u llvm/test/Programs/Makefile.programs:1.21 llvm/test/Programs/Makefile.programs:1.22
--- llvm/test/Programs/Makefile.programs:1.21	Sun Jan 12 18:53:13 2003
+++ llvm/test/Programs/Makefile.programs	Thu Jan 16 14:27:30 2003
@@ -150,3 +150,28 @@
 Output/%.diff-cbe: Output/%.out-nat Output/%.out-cbe
 	$(DIFFPROG) cbe $(subst Output/,,$(@:.diff-cbe=))
 
+# Support for the TEST= option... when TEST= is specified on the command line,
+# the default target is the test target.  Here we dispatch to a specific set of
+# tests.
+#
+test:: $(addprefix test.$(TEST).,$(PROGRAMS_TO_TEST))
+
+# If they just say 'make test' then we print out an error telling the user to
+# specify a TEST= option.
+test..%:
+	@echo "***************************************************************"
+	@echo "ERROR: you cannot type '$(MAKE) test' directly."
+	@echo "Instead, use '$(MAKE) TEST=foo' where foo is the name of a test."
+	@echo "Tests should be defined in llvm/test/Programs/Makefile.TEST.*."
+	@echo "Alternatively, just use '$(MAKE)' to run comparisons."
+	@echo "***************************************************************"
+	@echo
+	@exit 1
+
+# Include all makefiles which define tests... These makefiles must define
+# test.<testname>.%  given input from Output/%.llvm.bc
+#
+TestMakefiles := $(wildcard $(LEVEL)/test/Programs/Makefile.TEST.*)
+ifneq ($(TestMakefiles),)
+-include $(TestMakefiles)
+endif