[llvm-commits] CVS: llvm/lib/Target/X86/MachineCodeEmitter.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

MachineCodeEmitter.cpp updated: 1.17 -> 1.18

---
Log message:

* Add support for FP registers ST*
* Add support for the constant pool & constant pool indices
* Add support for MRMS?m instructions



---
Diffs of the changes:

Index: llvm/lib/Target/X86/MachineCodeEmitter.cpp
diff -u llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.17 llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.18
--- llvm/lib/Target/X86/MachineCodeEmitter.cpp:1.17	Sat Dec 28 14:24:48 2002
+++ llvm/lib/Target/X86/MachineCodeEmitter.cpp	Mon Jan  6 12:49:24 2003
@@ -58,6 +58,7 @@
   II = &((X86TargetMachine&)MF.getTarget()).getInstrInfo();
 
   MCE.startFunction(MF);
+  MCE.emitConstantPool(MF.getConstantPool());
   for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
     emitBasicBlock(*I);
   MCE.finishFunction(MF);
@@ -91,6 +92,10 @@
   case X86::EBP: case X86::BP: case X86::CH: return N86::EBP;
   case X86::ESI: case X86::SI: case X86::DH: return N86::ESI;
   case X86::EDI: case X86::DI: case X86::BH: return N86::EDI;
+
+  case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
+  case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
+    return RegNo-X86::ST0;
   default:
     assert(RegNo >= MRegisterInfo::FirstVirtualRegister &&
            "Unknown physical register!");
@@ -128,6 +133,15 @@
 
 void Emitter::emitMemModRMByte(const MachineInstr &MI,
                                unsigned Op, unsigned RegOpcodeField) {
+  if (MI.getOperand(Op+3).isConstantPoolIndex()) {
+    // Emit a direct address reference [disp32] where the displacement is
+    // controlled by the MCE.
+    MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
+    unsigned Index = MI.getOperand(Op+3).getConstantPoolIndex();
+    MCE.emitFunctionConstantValueAddress(Index);
+    return;
+  }
+
   const MachineOperand &BaseReg  = MI.getOperand(Op);
   const MachineOperand &Scale    = MI.getOperand(Op+1);
   const MachineOperand &IndexReg = MI.getOperand(Op+2);
@@ -233,17 +247,19 @@
     break;
   case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
   case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
-    MCE.emitByte(0xD8 + (Desc.TSFlags & X86II::Op0Mask)-X86II::D8);
+    MCE.emitByte(0xD8+
+		 (((Desc.TSFlags & X86II::Op0Mask)-X86II::D8)
+		                   >> X86II::Op0Shift));
     break; // Two-byte opcode prefix
-
-  default: break;  // No prefix!
+  default: assert(0 && "Invalid prefix!");
+  case 0: break;  // No prefix!
   }
 
   unsigned char BaseOpcode = II->getBaseOpcodeFor(Opcode);
   switch (Desc.TSFlags & X86II::FormMask) {
-  default: assert(0 && "Unknown FormMask value!");
+  default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
   case X86II::Pseudo:
-    std::cerr << "X86 Machine Code Emitter: Not emitting: " << MI;
+    std::cerr << "X86 Machine Code Emitter: No 'form', not emitting: " << MI;
     break;
   case X86II::RawFrm:
     MCE.emitByte(BaseOpcode);
@@ -297,6 +313,19 @@
     if (MI.getOperand(MI.getNumOperands()-1).isImmediate()) {
       unsigned Size = sizeOfPtr(Desc);
       emitConstant(MI.getOperand(MI.getNumOperands()-1).getImmedValue(), Size);
+    }
+    break;
+
+  case X86II::MRMS0m: case X86II::MRMS1m:
+  case X86II::MRMS2m: case X86II::MRMS3m:
+  case X86II::MRMS4m: case X86II::MRMS5m:
+  case X86II::MRMS6m: case X86II::MRMS7m: 
+    MCE.emitByte(BaseOpcode);
+    emitMemModRMByte(MI, 0, (Desc.TSFlags & X86II::FormMask)-X86II::MRMS0m);
+
+    if (MI.getNumOperands() == 5) {
+      unsigned Size = sizeOfPtr(Desc);
+      emitConstant(MI.getOperand(4).getImmedValue(), Size);
     }
     break;
   }