[llvm-commits] CVS: llvm/include/llvm/Target/TargetMachine.h TargetRegInfo.h TargetSchedInfo.h
Chris Lattner
lattner at cs.uiuc.edu
Sat Dec 28 21:14:35 PST 2002
Changes in directory llvm/include/llvm/Target:
TargetMachine.h updated: 1.27 -> 1.28
TargetRegInfo.h updated: 1.29 -> 1.30
TargetSchedInfo.h updated: 1.12 -> 1.13
---
Log message:
More renamings of Target/Machine*Info to Target/Target*Info
---
Diffs of the changes:
Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.27 llvm/include/llvm/Target/TargetMachine.h:1.28
--- llvm/include/llvm/Target/TargetMachine.h:1.27 Sat Dec 28 20:50:25 2002
+++ llvm/include/llvm/Target/TargetMachine.h Sat Dec 28 21:12:54 2002
@@ -12,8 +12,8 @@
class MachineInstrInfo;
class MachineInstrDescriptor;
-class MachineSchedInfo;
-class MachineRegInfo;
+class TargetSchedInfo;
+class TargetRegInfo;
class TargetFrameInfo;
class TargetCacheInfo;
class TargetOptInfo;
@@ -57,8 +57,8 @@
// -- Machine-level optimization information (peephole only)
//
virtual const MachineInstrInfo& getInstrInfo() const = 0;
- virtual const MachineSchedInfo& getSchedInfo() const = 0;
- virtual const MachineRegInfo& getRegInfo() const = 0;
+ virtual const TargetSchedInfo& getSchedInfo() const = 0;
+ virtual const TargetRegInfo& getRegInfo() const = 0;
virtual const TargetFrameInfo& getFrameInfo() const = 0;
virtual const TargetCacheInfo& getCacheInfo() const = 0;
virtual const TargetOptInfo& getOptInfo() const = 0;
Index: llvm/include/llvm/Target/TargetRegInfo.h
diff -u llvm/include/llvm/Target/TargetRegInfo.h:1.29 llvm/include/llvm/Target/TargetRegInfo.h:1.30
--- llvm/include/llvm/Target/TargetRegInfo.h:1.29 Sun Oct 27 20:27:07 2002
+++ llvm/include/llvm/Target/TargetRegInfo.h Sat Dec 28 21:12:54 2002
@@ -1,12 +1,12 @@
-//===-- llvm/Target/RegInfo.h - Target Register Information ------*- C++ -*-==//
+//===-- llvm/Target/TargetRegInfo.h - Target Register Info -------*- C++ -*-==//
//
// This file is used to describe the register system of a target to the
// register allocator.
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_MACHINEREGINFO_H
-#define LLVM_TARGET_MACHINEREGINFO_H
+#ifndef LLVM_TARGET_TARGETREGINFO_H
+#define LLVM_TARGET_TARGETREGINFO_H
#include "Support/NonCopyable.h"
#include "Support/hash_map"
@@ -24,17 +24,11 @@
class PhyRegAlloc;
class BasicBlock;
-//-----------------------------------------------------------------------------
-// class MachineRegClassInfo
-//
-// Purpose:
-// Interface to description of machine register class (e.g., int reg class
-// float reg class etc)
-//
-//--------------------------------------------------------------------------
-
-
-class MachineRegClassInfo {
+///----------------------------------------------------------------------------
+/// Interface to description of machine register class (e.g., int reg class
+/// float reg class etc)
+///
+class TargetRegClassInfo {
protected:
const unsigned RegClassID; // integer ID of a reg class
const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
@@ -51,31 +45,26 @@
std::vector<bool> &IsColorUsedArr) const = 0;
virtual bool isRegVolatile(int Reg) const = 0;
- MachineRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
+ TargetRegClassInfo(unsigned ID, unsigned NVR, unsigned NAR)
: RegClassID(ID), NumOfAvailRegs(NVR), NumOfAllRegs(NAR) {}
};
//---------------------------------------------------------------------------
-// class MachineRegInfo
-//
-// Purpose:
-// Interface to register info of target machine
-//
-//--------------------------------------------------------------------------
-
-class MachineRegInfo : public NonCopyableV {
+/// TargetRegInfo - Interface to register info of target machine
+///
+class TargetRegInfo : public NonCopyableV {
protected:
// A vector of all machine register classes
//
- std::vector<const MachineRegClassInfo *> MachineRegClassArr;
+ std::vector<const TargetRegClassInfo *> MachineRegClassArr;
public:
const TargetMachine ⌖
- MachineRegInfo(const TargetMachine& tgt) : target(tgt) { }
- ~MachineRegInfo() {
+ TargetRegInfo(const TargetMachine& tgt) : target(tgt) { }
+ ~TargetRegInfo() {
for (unsigned i = 0, e = MachineRegClassArr.size(); i != e; ++i)
delete MachineRegClassArr[i];
}
@@ -96,7 +85,7 @@
return MachineRegClassArr.size();
}
- const MachineRegClassInfo *getMachineRegClass(unsigned i) const {
+ const TargetRegClassInfo *getMachineRegClass(unsigned i) const {
return MachineRegClassArr[i];
}
@@ -136,7 +125,7 @@
// The following methods are used to generate "copy" machine instructions
- // for an architecture. Currently they are used in MachineRegClass
+ // for an architecture. Currently they are used in TargetRegClass
// interface. However, they can be moved to MachineInstrInfo interface if
// necessary.
//
Index: llvm/include/llvm/Target/TargetSchedInfo.h
diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.12 llvm/include/llvm/Target/TargetSchedInfo.h:1.13
--- llvm/include/llvm/Target/TargetSchedInfo.h:1.12 Mon Oct 28 17:54:23 2002
+++ llvm/include/llvm/Target/TargetSchedInfo.h Sat Dec 28 21:12:54 2002
@@ -1,11 +1,11 @@
-//===- Target/MachineSchedInfo.h - Target Instruction Sched Info -*- C++ -*-==//
+//===- Target/TargetSchedInfo.h - Target Instruction Sched Info --*- C++ -*-==//
//
// This file describes the target machine to the instruction scheduler.
//
//===----------------------------------------------------------------------===//
-#ifndef LLVM_TARGET_MACHINESCHEDINFO_H
-#define LLVM_TARGET_MACHINESCHEDINFO_H
+#ifndef LLVM_TARGET_TARGETSCHEDINFO_H
+#define LLVM_TARGET_TARGETSCHEDINFO_H
#include "llvm/Target/MachineInstrInfo.h"
#include "Support/hash_map"
@@ -164,19 +164,15 @@
feasibleSlots.resize(maxNumSlots);
}
- friend class MachineSchedInfo; // give access to these functions
+ friend class TargetSchedInfo; // give access to these functions
};
//---------------------------------------------------------------------------
-// class MachineSchedInfo
-//
-// Purpose:
-// Common interface to machine information for instruction scheduling
-//---------------------------------------------------------------------------
-
-class MachineSchedInfo {
-public:
+/// TargetSchedInfo - Common interface to machine information for
+/// instruction scheduling
+///
+struct TargetSchedInfo {
const TargetMachine& target;
unsigned maxNumIssueTotal;
@@ -203,17 +199,17 @@
}
private:
- MachineSchedInfo(const MachineSchedInfo &); // DO NOT IMPLEMENT
- void operator=(const MachineSchedInfo &); // DO NOT IMPLEMENT
+ TargetSchedInfo(const TargetSchedInfo &); // DO NOT IMPLEMENT
+ void operator=(const TargetSchedInfo &); // DO NOT IMPLEMENT
public:
- /*ctor*/ MachineSchedInfo (const TargetMachine& tgt,
+ /*ctor*/ TargetSchedInfo (const TargetMachine& tgt,
int _numSchedClasses,
const InstrClassRUsage* _classRUsages,
const InstrRUsageDelta* _usageDeltas,
const InstrIssueDelta* _issueDeltas,
unsigned _numUsageDeltas,
unsigned _numIssueDeltas);
- /*dtor*/ virtual ~MachineSchedInfo () {}
+ /*dtor*/ virtual ~TargetSchedInfo() {}
inline const MachineInstrInfo& getInstrInfo() const {
return *mii;
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