[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterClasses.cpp X86RegisterInfo.def
Chris Lattner
lattner at cs.uiuc.edu
Tue Dec 24 23:09:00 PST 2002
Changes in directory llvm/lib/Target/X86:
X86RegisterClasses.cpp updated: 1.8 -> 1.9
X86RegisterInfo.def updated: 1.10 -> 1.11
---
Log message:
Initial support for FP registers
---
Diffs of the changes:
Index: llvm/lib/Target/X86/X86RegisterClasses.cpp
diff -u llvm/lib/Target/X86/X86RegisterClasses.cpp:1.8 llvm/lib/Target/X86/X86RegisterClasses.cpp:1.9
--- llvm/lib/Target/X86/X86RegisterClasses.cpp:1.8 Mon Dec 16 22:19:17 2002
+++ llvm/lib/Target/X86/X86RegisterClasses.cpp Tue Dec 24 23:08:03 2002
@@ -9,6 +9,9 @@
#include "llvm/Type.h"
#include "X86.h"
+//===----------------------------------------------------------------------===//
+// 8 Bit Integer Registers
+//
namespace {
const unsigned ByteRegClassRegs[] = {
#define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
@@ -18,8 +21,8 @@
TargetRegisterClass X86ByteRegisterClassInstance(1, ByteRegClassRegs,
ByteRegClassRegs+sizeof(ByteRegClassRegs)/sizeof(ByteRegClassRegs[0]));
-//
-//
+//===----------------------------------------------------------------------===//
+// 16 Bit Integer Registers
//
const unsigned ShortRegClassRegs[] = {
#define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
@@ -29,10 +32,9 @@
TargetRegisterClass X86ShortRegisterClassInstance(2, ShortRegClassRegs,
ShortRegClassRegs+sizeof(ShortRegClassRegs)/sizeof(ShortRegClassRegs[0]));
+//===----------------------------------------------------------------------===//
+// 32 Bit Integer Registers
//
-//
-//
-
const unsigned IntRegClassRegs[] = {
#define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
#include "X86RegisterInfo.def"
@@ -41,10 +43,25 @@
TargetRegisterClass X86IntRegisterClassInstance(4, IntRegClassRegs,
IntRegClassRegs+sizeof(IntRegClassRegs)/sizeof(IntRegClassRegs[0]));
+//===----------------------------------------------------------------------===//
+// Pseudo Floating Point Registers
+//
+ const unsigned PFPRegClassRegs[] = {
+#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
+#include "X86RegisterInfo.def"
+ };
+
+ TargetRegisterClass X86FPRegisterClassInstance(10, PFPRegClassRegs,
+ PFPRegClassRegs+sizeof(PFPRegClassRegs)/sizeof(PFPRegClassRegs[0]));
+
+//===----------------------------------------------------------------------===//
+// Register class array...
+//
const TargetRegisterClass * const X86RegClasses[] = {
&X86ByteRegisterClassInstance,
&X86ShortRegisterClassInstance,
- &X86IntRegisterClassInstance
+ &X86IntRegisterClassInstance,
+ &X86FPRegisterClassInstance,
};
}
@@ -72,26 +89,23 @@
-const TargetRegisterClass* X86RegisterInfo::getRegClassForType(const Type* Ty)
- const {
+const TargetRegisterClass*
+X86RegisterInfo::getRegClassForType(const Type* Ty) const {
switch (Ty->getPrimitiveID()) {
+ default: assert(0 && "Invalid type to getClass!");
case Type::BoolTyID:
case Type::SByteTyID:
case Type::UByteTyID: return &X86ByteRegisterClassInstance;
case Type::ShortTyID:
case Type::UShortTyID: return &X86ShortRegisterClassInstance;
- case Type::LongTyID: // None of these are handled yet!
- case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus!
+ case Type::LongTyID: // FIXME: Longs are not handled yet!
+ case Type::ULongTyID: // FIXME: Treat these like ints, this is bogus!
case Type::IntTyID:
case Type::UIntTyID:
case Type::PointerTyID: return &X86IntRegisterClassInstance;
case Type::FloatTyID:
- case Type::DoubleTyID:
-
- default:
- assert(0 && "Invalid type to getClass!");
- return 0; // not reached
+ case Type::DoubleTyID: return &X86FPRegisterClassInstance;
}
}
Index: llvm/lib/Target/X86/X86RegisterInfo.def
diff -u llvm/lib/Target/X86/X86RegisterInfo.def:1.10 llvm/lib/Target/X86/X86RegisterInfo.def:1.11
--- llvm/lib/Target/X86/X86RegisterInfo.def:1.10 Mon Dec 16 13:31:48 2002
+++ llvm/lib/Target/X86/X86RegisterInfo.def Tue Dec 24 23:08:03 2002
@@ -27,6 +27,18 @@
R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
+// Pseudo Floating Point registers
+#ifndef PFP
+#define PFP(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
+ R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
+#endif
+
+// Floating Point Stack registers
+#ifndef FPS
+#define FPS(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
+ R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
+#endif
+
// Arguments passed into the R macros
// #1: Enum Name - This ends up being a symbol in the X86 namespace
// #2: Register name - The name of the register as used by the gnu assembler
@@ -69,14 +81,33 @@
R16( DI, "DI" , MRF::INT16, 0, A_DI)
// 8 bit registers aliased with registers above as well
- R8 ( AL, "AL" , MRF::INT8 , 0, A_AL)
- R8 ( CL, "CL" , MRF::INT8 , 0, A_CL)
- R8 ( DL, "DL" , MRF::INT8 , 0, A_DL)
- R8 ( BL, "BL" , MRF::INT8 , 0, A_BL)
- R8 ( AH, "AH" , MRF::INT8 , 0, A_AH)
- R8 ( CH, "CH" , MRF::INT8 , 0, A_CH)
- R8 ( DH, "DH" , MRF::INT8 , 0, A_DH)
- R8 ( BH, "BH" , MRF::INT8 , 0, A_BH)
+R8 ( AL, "AL" , MRF::INT8 , 0, A_AL)
+R8 ( CL, "CL" , MRF::INT8 , 0, A_CL)
+R8 ( DL, "DL" , MRF::INT8 , 0, A_DL)
+R8 ( BL, "BL" , MRF::INT8 , 0, A_BL)
+R8 ( AH, "AH" , MRF::INT8 , 0, A_AH)
+R8 ( CH, "CH" , MRF::INT8 , 0, A_CH)
+R8 ( DH, "DH" , MRF::INT8 , 0, A_DH)
+R8 ( BH, "BH" , MRF::INT8 , 0, A_BH)
+
+// Pseudo Floating Point Registers
+PFP(FP0, "fp0", MRF::FP80 , 0, 0 /*noalias*/)
+PFP(FP1, "fp1", MRF::FP80 , 0, 0 /*noalias*/)
+PFP(FP2, "fp2", MRF::FP80 , 0, 0 /*noalias*/)
+PFP(FP3, "fp3", MRF::FP80 , 0, 0 /*noalias*/)
+PFP(FP4, "fp4", MRF::FP80 , 0, 0 /*noalias*/)
+PFP(FP5, "fp5", MRF::FP80 , 0, 0 /*noalias*/)
+PFP(FP6, "fp6", MRF::FP80 , 0, 0 /*noalias*/)
+
+// Floating point stack registers
+FPS(ST0, "ST(0)", MRF::FP80, 0, 0)
+FPS(ST1, "ST(1)", MRF::FP80, 0, 0)
+FPS(ST2, "ST(2)", MRF::FP80, 0, 0)
+FPS(ST3, "ST(3)", MRF::FP80, 0, 0)
+FPS(ST4, "ST(4)", MRF::FP80, 0, 0)
+FPS(ST5, "ST(5)", MRF::FP80, 0, 0)
+FPS(ST6, "ST(6)", MRF::FP80, 0, 0)
+FPS(ST7, "ST(7)", MRF::FP80, 0, 0)
// Flags, Segment registers, etc...
@@ -126,3 +157,5 @@
#undef R8
#undef R16
#undef R32
+#undef PFP
+#undef FPS
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