[llvm-commits] CVS: llvm/lib/Target/X86/X86RegisterClasses.cpp X86RegisterInfo.cpp X86RegisterInfo.def X86.h
Chris Lattner
lattner at cs.uiuc.edu
Mon Dec 16 10:16:00 PST 2002
Changes in directory llvm/lib/Target/X86:
X86RegisterClasses.cpp updated: 1.6 -> 1.7
X86RegisterInfo.cpp updated: 1.16 -> 1.17
X86RegisterInfo.def updated: 1.8 -> 1.9
X86.h updated: 1.9 -> 1.10
---
Log message:
Try #2 to get alias set stuff to work
---
Diffs of the changes:
Index: llvm/lib/Target/X86/X86RegisterClasses.cpp
diff -u llvm/lib/Target/X86/X86RegisterClasses.cpp:1.6 llvm/lib/Target/X86/X86RegisterClasses.cpp:1.7
--- llvm/lib/Target/X86/X86RegisterClasses.cpp:1.6 Mon Dec 16 09:55:25 2002
+++ llvm/lib/Target/X86/X86RegisterClasses.cpp Mon Dec 16 10:14:51 2002
@@ -11,7 +11,7 @@
namespace {
const unsigned ByteRegClassRegs[] = {
-#define R8(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) X86::ENUM,
+#define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
#include "X86RegisterInfo.def"
};
@@ -22,7 +22,7 @@
//
//
const unsigned ShortRegClassRegs[] = {
-#define R16(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) X86::ENUM,
+#define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
#include "X86RegisterInfo.def"
};
@@ -34,7 +34,7 @@
//
const unsigned IntRegClassRegs[] = {
-#define R32(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) X86::ENUM,
+#define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) X86::ENUM,
#include "X86RegisterInfo.def"
};
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.16 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.17
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.16 Mon Dec 16 09:55:25 2002
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Mon Dec 16 10:14:51 2002
@@ -16,7 +16,7 @@
// descriptors
//
static const MRegisterDesc X86Regs[] = {
-#define R(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) { NAME, FLAGS, TSFLAGS },
+#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) { NAME, FLAGS, TSFLAGS },
#include "X86RegisterInfo.def"
};
Index: llvm/lib/Target/X86/X86RegisterInfo.def
diff -u llvm/lib/Target/X86/X86RegisterInfo.def:1.8 llvm/lib/Target/X86/X86RegisterInfo.def:1.9
--- llvm/lib/Target/X86/X86RegisterInfo.def:1.8 Mon Dec 16 09:57:44 2002
+++ llvm/lib/Target/X86/X86RegisterInfo.def Mon Dec 16 10:14:51 2002
@@ -9,22 +9,22 @@
// NOTE: No include guards desired
#ifndef R
-#define R(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3)
+#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
#ifndef R8
-#define R8(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) \
- R(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3)
+#define R8(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
+ R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
#ifndef R16
-#define R16(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) \
- R(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3)
+#define R16(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
+ R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
#ifndef R32
-#define R32(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) \
- R(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3)
+#define R32(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) \
+ R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET)
#endif
// Arguments passed into the R macros
@@ -34,8 +34,7 @@
// MRegisterInfo.h file.
// #4: Target Specific Flags - Another bitfield containing X86 specific flags
// as neccesary.
-//
-// #5,6,7: Registers aliased to this register, or 0 if none.
+// #5: Alias set for registers aliased to this register (sets defined below).
// The first register must always be a 'noop' register for all backends. This
@@ -47,45 +46,79 @@
// The X86 backend uses this value as an operand register only in memory
// references where it means that there is no base or index register.
//
-R(NoReg,"none", 0, 0, 0, 0, 0)
+R(NoReg,"none", 0, 0, 0/*noalias*/)
// 32 bit registers, ordered as the processor does...
-R32(EAX, "EAX", MRF::INT32, 0, X86::AX, X86::AH, X86::AL)
-R32(ECX, "ECX", MRF::INT32, 0, X86::CX, X86::CH, X86::CL)
-R32(EDX, "EDX", MRF::INT32, 0, X86::DX, X86::DH, X86::DL)
-R32(EBX, "EBX", MRF::INT32, 0, X86::BX, X86::BH, X86::BL)
-R32(ESP, "ESP", MRF::INT32, 0, X86::SP, 0, 0)
-R32(EBP, "EBP", MRF::INT32, 0, X86::BP, 0, 0)
-R32(ESI, "ESI", MRF::INT32, 0, X86::SI, 0, 0)
-R32(EDI, "EDI", MRF::INT32, 0, X86::DI, 0, 0)
+R32(EAX, "EAX", MRF::INT32, 0, A_EAX)
+R32(ECX, "ECX", MRF::INT32, 0, A_ECX)
+R32(EDX, "EDX", MRF::INT32, 0, A_EDX)
+R32(EBX, "EBX", MRF::INT32, 0, A_EBX)
+R32(ESP, "ESP", MRF::INT32, 0, A_ESP)
+R32(EBP, "EBP", MRF::INT32, 0, A_EBP)
+R32(ESI, "ESI", MRF::INT32, 0, A_ESI)
+R32(EDI, "EDI", MRF::INT32, 0, A_EDI)
// 16 bit registers, aliased with the corresponding 32 bit registers above
-R16( AX, "AX" , MRF::INT16, 0, X86::EAX, X86::AH, X86::AL)
-R16( CX, "CX" , MRF::INT16, 0, X86::ECX, X86::CH, X86::CL)
-R16( DX, "DX" , MRF::INT16, 0, X86::EDX, X86::DH, X86::DL)
-R16( BX, "BX" , MRF::INT16, 0, X86::EBX, X86::BH, X86::BL)
-R16( SP, "SP" , MRF::INT16, 0, X86::ESP, 0, 0)
-R16( BP, "BP" , MRF::INT16, 0, X86::EBP, 0, 0)
-R16( SI, "SI" , MRF::INT16, 0, X86::ESI, 0, 0)
-R16( DI, "DI" , MRF::INT16, 0, X86::EDI, 0, 0)
+R16( AX, "AX" , MRF::INT16, 0, A_AX)
+R16( CX, "CX" , MRF::INT16, 0, A_CX)
+R16( DX, "DX" , MRF::INT16, 0, A_DX)
+R16( BX, "BX" , MRF::INT16, 0, A_BX)
+R16( SP, "SP" , MRF::INT16, 0, A_SP)
+R16( BP, "BP" , MRF::INT16, 0, A_BP)
+R16( SI, "SI" , MRF::INT16, 0, A_SI)
+R16( DI, "DI" , MRF::INT16, 0, A_DI)
// 8 bit registers aliased with registers above as well
-R8 ( AL, "AL" , MRF::INT8 , 0, X86::EAX, X86::AX, 0)
-R8 ( CL, "CL" , MRF::INT8 , 0, X86::ECX, X86::CX, 0)
-R8 ( DL, "DL" , MRF::INT8 , 0, X86::EDX, X86::DX, 0)
-R8 ( BL, "BL" , MRF::INT8 , 0, X86::EBX, X86::BX, 0)
-R8 ( AH, "AH" , MRF::INT8 , 0, X86::EAX, X86::AX, 0)
-R8 ( CH, "CH" , MRF::INT8 , 0, X86::ECX, X86::CX, 0)
-R8 ( DH, "DH" , MRF::INT8 , 0, X86::EDX, X86::DX, 0)
-R8 ( BH, "BH" , MRF::INT8 , 0, X86::EBX, X86::BX, 0)
+ R8 ( AL, "AL" , MRF::INT8 , 0, A_AL)
+ R8 ( CL, "CL" , MRF::INT8 , 0, A_CL)
+ R8 ( DL, "DL" , MRF::INT8 , 0, A_DL)
+ R8 ( BL, "BL" , MRF::INT8 , 0, A_BL)
+ R8 ( AH, "AH" , MRF::INT8 , 0, A_AH)
+ R8 ( CH, "CH" , MRF::INT8 , 0, A_CH)
+ R8 ( DH, "DH" , MRF::INT8 , 0, A_DH)
+ R8 ( BH, "BH" , MRF::INT8 , 0, A_BH)
// Flags, Segment registers, etc...
// This is a slimy hack to make it possible to say that flags are clobbered...
// Ideally we'd model instructions based on which particular flag(s) they
// could clobber.
-R(EFLAGS, "EFLAGS", MRF::INT16, 0, 0, 0, 0)
+R(EFLAGS, "EFLAGS", MRF::INT16, 0, 0 /*noalias*/)
+
+
+//===----------------------------------------------------------------------===//
+// Register alias set handling...
+//
+
+// Macro to handle definitions of alias sets that registers use...
+#ifndef ALIASLIST
+#define ALIASLIST(NAME, ...)
+#endif
+ALIASLIST(A_EAX , X86::AX, X86::AH, X86::AL, 0)
+ALIASLIST(A_ECX , X86::CX, X86::CH, X86::CL, 0)
+ALIASLIST(A_EDX , X86::DX, X86::DH, X86::DL, 0)
+ALIASLIST(A_EBX , X86::BX, X86::BH, X86::BL, 0)
+ALIASLIST(A_ESP , X86::SP, 0)
+ALIASLIST(A_EBP , X86::BP, 0)
+ALIASLIST(A_ESI , X86::SI, 0)
+ALIASLIST(A_EDI , X86::DI, 0)
+ALIASLIST(A_AX , X86::EAX, X86::AH, X86::AL, 0)
+ALIASLIST(A_CX , X86::ECX, X86::CH, X86::CL, 0)
+ALIASLIST(A_DX , X86::EDX, X86::DH, X86::DL, 0)
+ALIASLIST(A_BX , X86::EBX, X86::BH, X86::BL, 0)
+ALIASLIST(A_SP , X86::ESP, 0)
+ALIASLIST(A_BP , X86::EBP, 0)
+ALIASLIST(A_SI , X86::ESI, 0)
+ALIASLIST(A_DI , X86::EDI, 0)
+ALIASLIST(A_AL , X86::EAX, X86::AX, 0)
+ALIASLIST(A_CL , X86::ECX, X86::CX, 0)
+ALIASLIST(A_DL , X86::EDX, X86::DX, 0)
+ALIASLIST(A_BL , X86::EBX, X86::BX, 0)
+ALIASLIST(A_AH , X86::EAX, X86::AX, 0)
+ALIASLIST(A_CH , X86::ECX, X86::CX, 0)
+ALIASLIST(A_DH , X86::EDX, X86::DX, 0)
+ALIASLIST(A_BH , X86::EBX, X86::BX, 0)
// We are now done with the R* macros
#undef R
Index: llvm/lib/Target/X86/X86.h
diff -u llvm/lib/Target/X86/X86.h:1.9 llvm/lib/Target/X86/X86.h:1.10
--- llvm/lib/Target/X86/X86.h:1.9 Mon Dec 16 09:55:51 2002
+++ llvm/lib/Target/X86/X86.h Mon Dec 16 10:14:51 2002
@@ -47,7 +47,7 @@
// mapping from register name to register number.
//
enum Register {
-#define R(ENUM, NAME, FLAGS, TSFLAGS, A1, A2, A3) ENUM,
+#define R(ENUM, NAME, FLAGS, TSFLAGS, ALIAS_SET) ENUM,
#include "X86RegisterInfo.def"
};
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