[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/main.cpp salloc.cpp salloc.h sparc9.hp sparcbin.cpp sparcbin.h analyze.cpp analyze.h bitmath.h fvector.h machine.h sparcdis.cpp sparcdis.h BinInterface.cpp BinInterface.h sparc.cpp sparc9.h test1.cpp
Cameron Buschardt
buschard at cs.uiuc.edu
Wed Nov 27 21:12:00 PST 2002
Changes in directory llvm/lib/Reoptimizer/BinInterface:
main.cpp added (r1.1)
salloc.cpp added (r1.1)
salloc.h added (r1.1)
sparc9.hp added (r1.1)
sparcbin.cpp added (r1.1)
sparcbin.h added (r1.1)
analyze.cpp updated: 1.3 -> 1.4
analyze.h updated: 1.2 -> 1.3
bitmath.h updated: 1.2 -> 1.3
fvector.h updated: 1.2 -> 1.3
machine.h updated: 1.2 -> 1.3
sparcdis.cpp updated: 1.3 -> 1.4
sparcdis.h updated: 1.2 -> 1.3
BinInterface.cpp (r1.2) removed
BinInterface.h (r1.2) removed
sparc.cpp (r1.3) removed
sparc9.h (r1.5) removed
test1.cpp (r1.2) removed
---
Log message:
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/BinInterface/analyze.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.3 llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.4
--- llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.3 Mon Nov 18 16:39:11 2002
+++ llvm/lib/Reoptimizer/BinInterface/analyze.cpp Wed Nov 27 20:19:49 2002
@@ -1,201 +1,324 @@
-//===-----------------------------------------------------------*- C++ -*--===//
-// SPARC Instruction Analyzer
+//*****************************************************************************
+// SPARC Instruction Analysis
//
-// Implementation of Analysis API
+// Analysis API Implementation
//
-// * Need to add support for register conditional branches
+// * Initial implementation
+// * Fixed API to handle the special case where RD can be read from
+// * Extended API to handle register read/write to G0 differently
+//
+// TODO:
+// * Floating point support is lacking
+// * Verify all instructions are supported (double check disasm tool too)
//
// 2002 Cameron Buschardt
-//===----------------------------------------------------------------------===//
+//*****************************************************************************
#include <stdio.h>
#include <stdlib.h>
+
+#include "sparc9.hp" // SPARC 9 opcode and field definitions
+#include "bitmath.h"
+#include "analyze.h" // API library
#include <assert.h>
-#include "sparc9.h"
-#include "analyze.h"
+//
+// Analyze instructions with OP field set to OP_BRANCH
+// (note not all of these instructions are branches!)
+//
unsigned sparc_analyzebr(unsigned instr)
{
- // look at the OP2 field
- if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
- {
- if (RD_FLD(instr, INSTR_RD) == 0)
- return 0; // This is the special encoding for NOP
- else
- return IF_RD;
- }
- else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
- {
- return IF_RCC | IF_BR;
- }
- else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
- return IF_RCC;
- else{
- printf("Unknown:OP=0b00 OP2 = 0x%04X\n", RD_FLD(instr, INSTR_OP2));
- assert(0);
- return 0;
- }
+ // look at the OP2 field
+ if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
+ {
+ // The sethi instruction zeroes the register
+ // and loads the immediate into bits 10->31
+ if (RD_FLD(instr, INSTR_RD) == 0)
+ return 0; // This is the special encoding for NOP
+ else
+ return IF_RD | IF_W_RD;
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
+ {
+ // Branch on integer condition code
+ return IF_RCC | IF_BR;
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
+ {
+ // Branch on integer register with prediction
+ return IF_RCC | IF_RS1 | IF_R_RS1;
+ }
+ else{
+ // There are a few opcodes missing from this field,
+ // if we run into any of them we can add support
+ // most appear to be systems level instructions
+
+ printf("Unknown:OP=0b00 OP2 = 0x%04X\n", RD_FLD(instr, INSTR_OP2));
+ assert(0);
+ return 0;
+ }
}
+
+//
+// Analyze instructions with OP field set to 2
+//
unsigned sparc_analyze_c2(unsigned instr)
{
- switch(RD_FLD(instr, INSTR_OP3))
- {
- case OP3_DONERETRY:
- return 0;
-
- case OP3_FCMP:
- case OP3_FPU:
- assert(0);
- return 0;
-
- case OP3_FLUSHW: //OP=OP_2 I = 0
- return 0;
-
- case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> IF_RS2, I=1->simm13}
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RS1 | IF_RS2;
- else
- return IF_RS1;
-
- case OP3_JMPL: //OP=OP_2 RD, IF_RS1 {I=0-> IF_RS2, I=1->SIMM13}
- case OP3_ADD:
- case OP3_AND:
- case OP3_OR:
- case OP3_XOR:
- case OP3_SUB:
- case OP3_ANDN:
- case OP3_ORN:
- case OP3_XNOR:
- case OP3_MULX:
- case OP3_SDIVX:
- case OP3_UDIVX:
- case OP3_SLL:
- case OP3_SRL:
- case OP3_SRA:
- case OP3_SAVE:
- case OP3_RETURN:
- case OP3_RESTORE:
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD | IF_RS1 | IF_RS2;
- else
- return IF_RD | IF_RS1;
-
- case OP3_ADDC:
- case OP3_SUBC:
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD| IF_RS1 | IF_RS2 | IF_RCC;
- else
- return IF_RD| IF_RS1 | IF_RCC;
-
-
-
- case OP3_XNORcc:
- case OP3_ANDNcc:
- case OP3_ANDcc:
- case OP3_ADDcc:
- case OP3_ORcc:
- case OP3_ORNcc:
- case OP3_SUBcc:
- case OP3_XORcc:
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD | IF_RS1 | IF_RS2 | IF_WCC;
- else
- return IF_RD | IF_RS1 | IF_WCC;
-
- case OP3_ADDCcc:
- case OP3_SUBCcc:
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC;
- else
- return IF_RD | IF_RS1 | IF_WCC | IF_RCC;
-
- default:
- printf("Unknown:OP=0b10 OP3 = 0x%04X\n", RD_FLD(instr, INSTR_OP3));
- assert(0);
-
- }
+ switch(RD_FLD(instr, INSTR_OP3))
+ {
+ case OP3_DONERETRY:
+ assert(0); // This appears to be a system instruction
+ // either way though it acts like a branch
+ // and should NOT appear in an trace
+ return 0;
+
+ case OP3_FCMP:
+ case OP3_FPU:
+ assert(0); // TODO: Add support when we do floating point
+ // support!
+ return 0;
+
+ case OP3_FLUSHW: //OP=OP_2 I = 0
+ return 0; // Flush has no negative side effects
+
+ case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> IF_RS2, I=1->simm13}
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RS1 | IF_RS2 | IF_R_RS1 | IF_R_RS2;
+ else
+ return IF_RS1 | IF_R_RS1;
+
+ case OP3_JMPL: //OP=OP_2 RD, IF_RS1 {I=0-> IF_RS2, I=1->SIMM13}
+ case OP3_ADD:
+ case OP3_AND:
+ case OP3_OR:
+ case OP3_XOR:
+ case OP3_SUB:
+ case OP3_ANDN:
+ case OP3_ORN:
+ case OP3_XNOR:
+ case OP3_MULX:
+ case OP3_SDIVX:
+ case OP3_UDIVX:
+ case OP3_SLL:
+ case OP3_SRL:
+ case OP3_SRA:
+ case OP3_SAVE:
+ case OP3_RETURN:
+ case OP3_RESTORE:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RD | IF_RS1 | IF_RS2 | IF_R_RS1 | IF_R_RS2 | IF_W_RD;
+ else
+ return IF_RD | IF_RS1 | IF_W_RD | IF_R_RS1;
+
+ case OP3_ADDC:
+ case OP3_SUBC:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RD| IF_RS1 | IF_RS2 | IF_RCC | IF_W_RD | IF_R_RS1 | IF_R_RS2;
+ else
+ return IF_RD| IF_RS1 | IF_RCC | IF_W_RD | IF_R_RS1;
+
+
+
+ case OP3_XNORcc:
+ case OP3_ANDNcc:
+ case OP3_ANDcc:
+ case OP3_ADDcc:
+ case OP3_ORcc:
+ case OP3_ORNcc:
+ case OP3_SUBcc:
+ case OP3_XORcc:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_W_RD | IF_R_RS1 | IF_R_RS2;
+ else
+ return IF_RD | IF_RS1 | IF_WCC | IF_W_RD | IF_R_RS1;
+
+ case OP3_ADDCcc:
+ case OP3_SUBCcc:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC | IF_W_RD | IF_R_RS1 | IF_R_RS2;
+ else
+ return IF_RD | IF_RS1 | IF_WCC | IF_RCC | IF_W_RD | IF_R_RS1;
+
+ default:
+ printf("Unknown:OP=0b10 OP3 = 0x%04X\n", RD_FLD(instr, INSTR_OP3));
+ assert(0);
+
+ }
}
unsigned sparc_analyze3(unsigned instr)
{
- switch(RD_FLD(instr, INSTR_OP3))
- {
- //OP=OP_3 RD, IF_RS1 {I=0->IF_RS2, I=1->SIMM13}
- case OP3_STB:
- case OP3_STH:
- case OP3_STW:
- case OP3_STX:
- case OP3_LDSB:
- case OP3_LDSH:
- case OP3_LDSW:
- case OP3_LDUB:
- case OP3_LDUH:
- case OP3_LDUW:
- case OP3_LDX:
- case OP3_LDSTUB:
- case OP3_STFA:
- case OP3_STDFA:
- case OP3_STQFA:
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RD | IF_RS1 | IF_RS2;
- else
- return IF_RD | IF_RS1;
-
- case OP3_CASXA:
- case OP3_CASA:
- return IF_RD | IF_RS1 | IF_RS2;
-
- case OP3_PREFETCHA:
- case OP3_PREFETCH:
- if (RD_FLD(instr, INSTR_I) == 0)
- return IF_RS1 | IF_RS2;
- else
- return IF_RS1;
+ switch(RD_FLD(instr, INSTR_OP3))
+ {
+ //OP=OP_3 RD, IF_RS1 {I=0->IF_RS2, I=1->SIMM13}
+ // BUG FIX! ST* does not write to RD, rather it reads!!
+ case OP3_STB:
+ case OP3_STH:
+ case OP3_STW:
+ case OP3_STX:
+
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RD | IF_RS1 | IF_RS2 | IF_R_RS1 | IF_R_RS2 | IF_R_RD;
+ else
+ return IF_RD | IF_RS1 | IF_R_RS1 | IF_R_RS2 | IF_R_RD;
+
+ case OP3_STFA:
+ case OP3_STDFA:
+ case OP3_STQFA:
+ assert(0);
+ return 0;
+
+ case OP3_LDSB:
+ case OP3_LDSH:
+ case OP3_LDSW:
+ case OP3_LDUB:
+ case OP3_LDUH:
+ case OP3_LDUW:
+ case OP3_LDX:
+ case OP3_LDSTUB:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RD | IF_RS1 | IF_RS2 | IF_W_RD | IF_R_RS1 | IF_R_RS2;
+ else
+ return IF_RD | IF_RS1 | IF_W_RD | IF_R_RS1;
+
+
+ // compare and exchange r[rd] with value at r[rs1] depending on
+ // comparison between r[rs1] and r[rs2]
+ case OP3_CASXA:
+ case OP3_CASA:
+ return IF_RD | IF_RS1 | IF_RS2 | IF_W_RD | IF_R_RD | IF_RS1 | IF_RS2;
+
+ // Cache line prefetch instructions
+ case OP3_PREFETCHA:
+ case OP3_PREFETCH:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ return IF_RS1 | IF_RS2 | IF_R_RS1 | IF_R_RS2;
+ else
+ return IF_RS1 | IF_R_RS1;
+
+ default:
+ printf("Unknown OP_3: OP3 = %08X\n", RD_FLD(instr, INSTR_OP3));
+ assert(0);
+ }
+}
- default:
- printf("Unknown OP_3: OP3 = %08X\n", RD_FLD(instr, INSTR_OP3));
- assert(0);
- }
+unsigned sparc_analyze_full(unsigned instr)
+{
+ if (RD_FLD(instr,INSTR_OP)==OP_2)
+ return sparc_analyze_c2(instr);
+ else if (RD_FLD(instr,INSTR_OP)==OP_3)
+ return sparc_analyze3(instr);
+ else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+ return sparc_analyzebr(instr);
+ else
+ return IF_CALL; // Call instruction not seen as branch
+ // in that control flow change is transparent
+ // to trace
}
unsigned sparc_analyze(unsigned instr)
{
- if (RD_FLD(instr,INSTR_OP)==OP_2)
- return sparc_analyze_c2(instr);
- else if (RD_FLD(instr,INSTR_OP)==OP_3)
- return sparc_analyze3(instr);
- else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
- return sparc_analyzebr(instr);
- else
- return 0;
+ unsigned flags = sparc_analyze_full(instr);
+
+ // validate that none of these registers are R0 if
+ // they are cancel read or write flags on that field
+
+ if (flags & IF_RS1)
+ if (!RD_FLD(instr, INSTR_RS1))
+ flags &= ~IF_R_RS1;
+ if (flags & IF_RS2)
+ if (!RD_FLD(instr, INSTR_RS2))
+ flags &= ~IF_R_RS2;
+
+ if (flags & IF_RD)
+ if (!RD_FLD(instr, INSTR_RD))
+ flags &= ~(IF_R_RD | IF_W_RD);
+
+ return flags;
}
-// returns which register is written to
unsigned sparc_getwrites(unsigned mask, unsigned instr)
{
- if (mask & IF_RD)
- return (1 << RD_FLD(instr, INSTR_RD));
- else
- return 0;
+ if (mask & IF_RD)
+ return (1 << RD_FLD(instr, INSTR_RD));
+ else
+ return 0;
}
-// returns which registers are read
unsigned sparc_getreads (unsigned mask, unsigned instr)
{
- unsigned m = 0;
-
- if (mask & IF_RS1)
- m |= (1 << RD_FLD(instr, INSTR_RS1));
+ unsigned m = 0;
+
+ if (mask & IF_RS1)
+ m |= (1 << RD_FLD(instr, INSTR_RS1));
- if (mask & IF_RS2)
- m |= (1 << RD_FLD(instr, INSTR_RS2));
+ if (mask & IF_RS2)
+ m |= (1 << RD_FLD(instr, INSTR_RS2));
- return m;
+ return m;
}
-// bit 0 -> CC READ , bit 1 -> CC write
-unsigned sparc_getcc (unsigned mask, unsigned instr)
+unsigned sparc_getcc (unsigned mask, unsigned instr) // bit 0 -> CC READ , bit 1 -> CC write
{
- return (mask & (IF_WCC | IF_RCC));
+ return (mask & (IF_WCC | IF_RCC));
+}
+
+//
+// Complete list of instructions that require relocation:
+// BPr -> D16LO/D16HI field
+// FBfcc -> DISP22 field (deprecated)
+// FBPfcc-> DISP19 field
+// Bicc -> DISP22 field (deprecated)
+// BPcc -> DISP19 field
+// CALL -> DISP30 field
+
+// returns relative branch destination (in instruction words)
+signed sparc_getbrdest(unsigned instr)
+{
+ if (RD_FLD(instr, INSTR_OP)==OP_CALL)
+ return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP30),30);
+ else
+ {
+ assert(RD_FLD(instr,INSTR_OP)==OP_BRANCH);
+ switch(RD_FLD(instr, INSTR_OP2))
+ {
+ case OP2_BPR: // D16LO/D16HI
+ return SIGN_EXTEND(RD_D16(instr), 16);
+ case OP2_BICC: // DISP22 field
+ case OP2_FB: // DISP22 field
+ return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP22), 22);
+ case OP2_FBP: // DISP19 field
+ case OP2_BPICC: // DISP19 field
+ return SIGN_EXTEND(RD_FLD(instr, INSTR_DISP19), 19);
+ default:
+ assert(0);
+ }
+
+ }
+}
+
+unsigned sparc_setbrdest(unsigned instr, signed reladdr)
+{
+
+ if (RD_FLD(instr,INSTR_OP)==OP_CALL)
+ return MK_FLD(INSTR_OP, OP_CALL) | MK_FLD(INSTR_DISP30, unsigned(reladdr) & 0x3FFFFFFF);
+ else
+ {
+ assert(RD_FLD(instr,INSTR_OP)==OP_BRANCH);
+ switch(RD_FLD(instr, INSTR_OP2))
+ {
+ case OP2_BPR: // D16LO/D16HI
+ return RM_FLD(INSTR_D16LO, RM_FLD(INSTR_D16HI, instr)) | MK_FLD(INSTR_D16LO, unsigned(reladdr) & 0x3FFF) | MK_FLD(INSTR_D16HI, (unsigned(reladdr) >> 14) & 3);
+
+ case OP2_BICC: // DISP22 field
+ case OP2_FB: // DISP22 field
+ return RM_FLD(INSTR_DISP22, instr) | MK_FLD(INSTR_DISP22, unsigned(reladdr) & 0x003FFFFF);
+ case OP2_FBP: // DISP19 field
+ case OP2_BPICC: // DISP19 field
+ return RM_FLD(INSTR_DISP19, instr) | MK_FLD(INSTR_DISP19, unsigned(reladdr) & 0x0007FFFF);
+ default:
+ assert(0);
+ }
+ }
}
Index: llvm/lib/Reoptimizer/BinInterface/analyze.h
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.h:1.2 llvm/lib/Reoptimizer/BinInterface/analyze.h:1.3
--- llvm/lib/Reoptimizer/BinInterface/analyze.h:1.2 Tue Nov 12 20:44:48 2002
+++ llvm/lib/Reoptimizer/BinInterface/analyze.h Wed Nov 27 20:19:50 2002
@@ -1,29 +1,53 @@
-//===-----------------------------------------------------------*- C++ -*--===//
-// SPARC Instruction Analyzer
+//*****************************************************************************
+// SPARC Instruction Analysis
//
-// Definitions of Analysis API
+// Analysis API Header
+//
+// * Initial implementation
+// * Fixed API to handle the special case where RD can be read from
+// * Extended API to handle register read/write to G0 differently
//
// 2002 Cameron Buschardt
-//===----------------------------------------------------------------------===//
+//*****************************************************************************
#ifndef __ANALYZE__
#define __ANALYZE__
-#define IF_RS1 1 // READ from RS1
-#define IF_RS2 2 // READ from RS2
-#define IF_RD 4 // WRITE to RC
-#define IF_BR 8 // BRANCH
-#define IF_WCC 16 // write to condition code
-#define IF_RCC 32 // read from condition code
-#define IF_USR 64 // first user IF instr
-// parse instruction
+#define IF_RS1 0x001 // Presence of RS1 field in instruction
+#define IF_RS2 0x002 // Presence of RS2 field in instruction
+#define IF_RD 0x004 // Presence of RD field in instruction
+#define IF_BR 0x008 // BRANCH
+#define IF_WCC 0x010 // write to condition code
+#define IF_RCC 0x020 // read from condition code
+#define IF_W_RD 0x040 // instruction writes rd
+#define IF_R_RD 0x080 // instruction reads rd (not exclusive with above)
+#define IF_R_RS1 0x100 // reads from RS1
+#define IF_R_RS2 0x200 // reads from RS2
+#define IF_CALL 0x400 // Is call instruction? (affects live registers)
+#define IF_USR 0x800 // Later in the code we wish to be able to pack other
+ // flags along side these when we store them in the
+ // SSA form. This is the first 'user' flag available
+
+/*
+ Important NOTE!
+
+ Since sparc treats register 0 specially - in such a way that
+ we wish to ignore writes or reads from this register for dataflow
+ analysis. IF_RS1, IF_RS2, and IF_RD are set independantly of whether
+ their respective register is 0 HOWEVER the read/write flags before are
+ turned off if their respective register is 0.
+
+*/
+
+// parse instruction and return IF flags
unsigned sparc_analyze(unsigned instr);
// use these command to expand the information return by analyze
unsigned sparc_getwrites(unsigned mask, unsigned instr);
unsigned sparc_getreads (unsigned mask, unsigned instr);
-// returns a bitmask containing RCC or WCC
-unsigned sparc_getcc (unsigned mask, unsigned instr);
+unsigned sparc_getcc (unsigned mask, unsigned instr); // returns a bitmask containing RCC or WCC
+unsigned sparc_setbrdest(unsigned instr, signed reladdr);
+signed sparc_getbrdest(unsigned instr);
-#endif
+#endif
\ No newline at end of file
Index: llvm/lib/Reoptimizer/BinInterface/bitmath.h
diff -u llvm/lib/Reoptimizer/BinInterface/bitmath.h:1.2 llvm/lib/Reoptimizer/BinInterface/bitmath.h:1.3
--- llvm/lib/Reoptimizer/BinInterface/bitmath.h:1.2 Wed Nov 13 14:17:52 2002
+++ llvm/lib/Reoptimizer/BinInterface/bitmath.h Wed Nov 27 20:19:51 2002
@@ -1,94 +1,115 @@
-//===-----------------------------------------------------------*- C++ -*--===//
-// High Performance Bit Utility Functions
+//*****************************************************************************
+//
+// High Performance Bit Utility Functions
//
//
// 2002 Cameron Buschardt
-//===----------------------------------------------------------------------===//
+//*****************************************************************************
#ifndef __BITMATH_H__
#define __BITMATH_H__
+//*********************************
+// Bitfield manipulation Macros
+//*********************************
+#define FLD_UPPER(FLD_DEF) (1 ? FLD_DEF)
+#define FLD_LOWER(FLD_DEF) (0 ? FLD_DEF)
+#define MASKBELOW(V) ((1 << V) - 1)
+#define MASKEQBELOW(V) ((1 << V) | MASKBELOW(V)) //masks off everything ABOVE
+#define RD_FLD(x, FLD) ((x & MASKEQBELOW(FLD_UPPER(FLD))) >> FLD_LOWER(FLD))
+#define MK_FLD(FLD, val) ((val << FLD_LOWER(FLD)) & MASKEQBELOW(FLD_UPPER(FLD)))
+#define MASK_FLD(FLD) (MASKEQBELOW(FLD_UPPER(FLD)) & ~MASKBELOW(FLD_LOWER(FLD)))
+#define RM_FLD(FLD, val) (val & ~(MASK_FLD(FLD)))
+
+//**********************************
+// Portable sign extend macros
+//**********************************
+#define SIGN_EXTEND13(x) (x & 0x1000 ? -(-x & 0x1FFF): x)
+#define SIGN_EXTEND(x, bits) (x & (1 << (bits-1)) ? -(-x & ((1 << bits)-1)):x)
+
#define IS_POWER_2(x) !(x & (x-1))
#define LOWEST_BIT(x) x & ~(x & (x-1))
#define UPPER_BITS(x) (x & (x-1))
// Good if expected number of bits set < 4
-inline static int countbits_sparse(unsigned m) //VALIDATED
+static int countbits_sparse(unsigned m) //VALIDATED
{
- int c = 0;
- while (m)
- {
- c++;
- m = UPPER_BITS(m);
- }
- return c;
+ int c = 0;
+ while (m)
+ {
+ c++;
+ m = UPPER_BITS(m);
+ }
+ return c;
}
-// base 2 sum of digits
-inline static int countbits_dense(unsigned w) //VALIDATED
+// base 2 sum of digits (hardwired for 32-bit)
+static int countbits_dense(unsigned w) //VALIDATED
{
- w = (0x55555555 & w) + (0x55555555 & (w >> 1));
- w = (0x33333333 & w) + (0x33333333 & (w >> 2));
- w = (w + (w>>4)) & 0x0f0f0f0f;
- w = w + (w>>16);
- w = w + (w>>8);
- return w&0xFF;
+ w = (0x55555555 & w) + (0x55555555 & (w >> 1));
+ w = (0x33333333 & w) + (0x33333333 & (w >> 2));
+ w = (w + (w>>4)) & 0x0f0f0f0f;
+ w = w + (w>>16);
+ w = w + (w>>8);
+ return w&0xFF;
}
-inline static bool ismod3(unsigned w) //VALIDATED
+static bool ismod3(unsigned w) //VALIDATED
{
- w = (w >> 16) + (w&0xFFFF);
- w = (w >> 8) + (w&0xFF);
- w = (w >> 4) + (w&0xF);
- w = (w >> 2) + (w&0x3);
- return (0xB6DB6DB6 >> w) & 1;
+ w = (w >> 16) + (w&0xFFFF);
+ w = (w >> 8) + (w&0xFF);
+ w = (w >> 4) + (w&0xF);
+ w = (w >> 2) + (w&0x3);
+ return (0xB6DB6DB6 >> w) & 1;
}
-inline static int mod3(unsigned w) //VALIDATED
+static int mod3(unsigned w) //VALIDATED
{
- w = (w >> 16) + (w&0xFFFF);
- w = (w >> 8) + (w&0xFF);
- w = (w >> 4) + (w&0xF);
- w = (w >> 2) + (w&0x3);
- //use lookuptable
- return (0x24924924 >> (w<<1)) & 3;
+ w = (w >> 16) + (w&0xFFFF);
+ w = (w >> 8) + (w&0xFF);
+ w = (w >> 4) + (w&0xF);
+ w = (w >> 2) + (w&0x3);
+ //use lookuptable
+ return (0x24924924 >> (w<<1)) & 3;
}
-inline static int parity(unsigned w) //VALIDATED
+static int parity(unsigned w) //VALIDATED
{
- w = w >> 16;
- w = w >> 8;
- w = w >> 4;
- w = w >> 2;
- w = w >> 1;
- return w & 1;
+ w ^= w >> 16;
+ w ^= w >> 8;
+ w ^= w >> 4;
+ w ^= w >> 2;
+ w ^= w >> 1;
+ return w & 1;
}
-inline static int log2(unsigned w) //VALIDATED
+static int log2(unsigned w) //VALIDATED
{
- int n = 0;
+ int n = 0;
- if (w >> 16)
- {
- w >>= 16;
- n+=16;
- }
- if (w >> 8)
- {
- w >>= 8;
- n+=8;
- }
- if (w >> 4)
- {
- w >>= 4;
- n+=4;
- }
+ if (w >> 16)
+ {
+ w >>= 16;
+ n+=16;
+ }
+ if (w >> 8)
+ {
+ w >>= 8;
+ n+=8;
+ }
+ if (w >> 4)
+ {
+ w >>= 4;
+ n+=4;
+ }
- w <<= 1;
- return ((0xFFFFAA50 >> w) & 3)+n;
+ w <<= 1;
+ return ((0xFFFFAA50 >> w) & 3)+n;
}
+
+
#endif
Index: llvm/lib/Reoptimizer/BinInterface/fvector.h
diff -u llvm/lib/Reoptimizer/BinInterface/fvector.h:1.2 llvm/lib/Reoptimizer/BinInterface/fvector.h:1.3
--- llvm/lib/Reoptimizer/BinInterface/fvector.h:1.2 Mon Nov 18 16:39:11 2002
+++ llvm/lib/Reoptimizer/BinInterface/fvector.h Wed Nov 27 20:19:51 2002
@@ -4,7 +4,7 @@
// * Implementation of a vector class around
// the stack allocator. Couldn't use STL
// because I need to support stored the
-// pointer to the allocator
+// pointer to the allocator stack.
//
// 2002 Cameron Buschardt
//*****************************************************************************
@@ -13,16 +13,19 @@
#define __FVECTOR_H__
#include "salloc.h"
+#include <assert.h>
+
template <class T>
class fvector
{
T * v_begin;
T * v_end;
T * v_capacity;
- Allocator * alloc;
+ StackAllocator * alloc;
void validate(T * pos)
{
+ assert(alloc);
if (pos < v_capacity)
return;
@@ -31,7 +34,7 @@
if (!ns)
ns = 64;
else
- while (ns < ms)
+ while (ns < ms)
ns *= 2;
T * n = (T *)alloc->resize(v_begin, sizeof(T) * ns);
@@ -40,9 +43,13 @@
v_begin = n;
}
+
fvector(const fvector &) {}
- operator = (const fvector &) {}
public:
+ typedef T * iterator;
+
+ iterator begin() { return v_begin; }
+ iterator end() { return v_end; }
void clear()
{
if (v_begin)
@@ -51,36 +58,57 @@
}
unsigned size() { return v_end - v_begin; }
- fvector(Allocator * a)
+
+ fvector(StackAllocator * a)
{
v_begin = v_end = v_capacity = NULL;
alloc = a;
}
+
+ fvector()
+ {
+ v_begin = v_end = v_capacity = NULL;
+ alloc = NULL;
+
+ }
+
+ void setallocator(StackAllocator * a)
+ {
+ assert(!alloc);
+ alloc = a;
+ }
void sizehint(unsigned v)
{
if (v_begin)
return;
- v_begin = (T*)alloc->alloc(sizeof(T) * v);
+ v_begin = (T*)alloc->alloc(sizeof(T) * v);
v_end = v_begin;
v_capacity = v_begin + v;
}
- void push_back(const T & e) {
- validate(v_end+1);
- *v_end++ = e;
+ void push_back(const T & e) {
+ validate(v_end+1);
+ *v_end++ = e;
}
- void inc(unsigned amt)
+ void inc(unsigned amt) // increase size by this amt
{
validate(v_end + amt);
v_end += amt;
}
+
+ void resize(unsigned amt)
+ {
+ validate(v_begin + amt);
+ v_end = v_begin + amt;
+ }
- T& operator[] (unsigned n) { return v_begin[n]; }
- const T & operator[] (unsigned n) const { return v_begin[n]; }
+ T& operator[] (unsigned n) { return v_begin[n]; }
+ const T & operator[] (unsigned n) const { return v_begin[n]; }
};
+
#endif
Index: llvm/lib/Reoptimizer/BinInterface/machine.h
diff -u llvm/lib/Reoptimizer/BinInterface/machine.h:1.2 llvm/lib/Reoptimizer/BinInterface/machine.h:1.3
--- llvm/lib/Reoptimizer/BinInterface/machine.h:1.2 Tue Nov 12 20:41:04 2002
+++ llvm/lib/Reoptimizer/BinInterface/machine.h Wed Nov 27 20:19:52 2002
@@ -9,9 +9,7 @@
#define __MACHINE_H__
#define MACHINE_CACHELINE 16
-#define FLIP_ENDIAN32(x) (((x & 255) << 24) \
- | (((x >> 8) & 255) << 16) \
- | (((x >> 16) & 255) << 8) \
- | ((x >> 24) & 255))
+#define FLIP_ENDIAN32(x) (((x & 255) << 24) | (((x >> 8) & 255) << 16) | (((x >> 16) & 255) << 8) | ((x >> 24) & 255))
-#endif
+
+#endif
\ No newline at end of file
Index: llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.3 llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.4
--- llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp:1.3 Wed Nov 13 14:17:52 2002
+++ llvm/lib/Reoptimizer/BinInterface/sparcdis.cpp Wed Nov 27 20:20:37 2002
@@ -1,479 +1,590 @@
-//===-----------------------------------------------------------*- C++ -*--===//
-// SPARC Disassembler
+//*****************************************************************************
+// SPARC Instruction Disassembler
//
+// Disassembler API Header
+//
+// * Initial implementation
+// * Added support for MOVcc (somehow I missed it?!)
+// * Added support for pseudo-disassembly
+// ( In the print routine for bin-interface we want
+// to be able to print the internal SSA form with
+// labels instead of registers. And we wish to
+// ommit RD from the view when we are not explicitly
+// reading from it)
+//
+// Todo:
+// * On the instructions that don't read from RD
+// do not print the label field (we get l-1 when we print)
//
// 2002 Cameron Buschardt
-//===----------------------------------------------------------------------===//
+//*****************************************************************************
#include <stdio.h>
#include <stdlib.h>
-#include "sparc9.h"
-void sparc_printbr(unsigned instr)
+#include "sparc9.hp" // SPARC 9 definitions
+#include "bitmath.h"
+#include <assert.h>
+
+void sparc_printbr(unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
{
- // look at the OP2 field
- if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP) {
- printf("ILLTRAP .. ");
- } else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI) {
- if (RD_FLD(instr, INSTR_RD) == 0)
- printf("NOP");
- else
- printf("SETHI %%hi(%08X), r%d",
- RD_FLD(instr, INSTR_IMM22) << 10, RD_FLD(instr, INSTR_RD));
- } else if (RD_FLD(instr, INSTR_OP2) == OP2_BICC) {
- printf("%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)],
- SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22));
- } else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR) {
- //A, RCOND_H, D16HI, P, RS1, D16LO
- printf("P%s%s%s r%d, %06X " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)],
- RD_FLD(instr, INSTR_A) ? ",a" : "",
- RD_FLD(instr, INSTR_P) ? ",pt" : ",pn",
- RD_FLD(instr, INSTR_RS1),
- RD_D16(instr)
- );
- } else if (RD_FLD(instr, INSTR_OP2)==OP2_FB) {
- // cond, A, disp22
- printf("%s%s %08X", fcond_names[RD_FLD(instr, INSTR_COND_H)],
- RD_FLD(instr, INSTR_A) ? ",a" : "",
- RD_FLD(instr, INSTR_DISP22));
- } else if (RD_FLD(instr, INSTR_OP2)==OP2_FBP) {
- //
- } else{
- printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2));
- }
+ // look at the OP2 field
+ if (RD_FLD(instr,INSTR_OP2)==OP2_ILLTRAP)
+ printf("ILLTRAP .. ");
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
+ {
+ if (RD_FLD(instr, INSTR_RD) == 0)
+ printf("NOP");
+ else
+ {
+ if (!labels)
+ printf("SETHI %%hi(%08X), r%d", RD_FLD(instr, INSTR_IMM22) << 10, RD_FLD(instr, INSTR_RD));
+ else
+ printf("SETHI %%hi(%08X), l%d", RD_FLD(instr, INSTR_IMM22) << 10, labelrd);
+ }
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
+ {
+ printf("%s disp:%08X",icond_names[RD_FLD(instr, INSTR_COND_H)], SIGN_EXTEND(RD_FLD(instr,INSTR_DISP22),22));
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
+ {
+ //A, RCOND_H, D16HI, P, RS1, D16LO
+ if (!labels)
+ {
+ printf("P%s%s%s r%d, %06X " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)],
+ RD_FLD(instr, INSTR_A) ? ",a" : "",
+ RD_FLD(instr, INSTR_P) ? ",pt" : ",pn",
+ RD_FLD(instr, INSTR_RS1),
+ RD_D16(instr)
+ );
+ }
+ else
+ {
+ printf("P%s%s%s l%d, %06X " , rcond_names[RD_FLD(instr, INSTR_RCOND_H)],
+ RD_FLD(instr, INSTR_A) ? ",a" : "",
+ RD_FLD(instr, INSTR_P) ? ",pt" : ",pn",
+ labelrs1,
+ RD_D16(instr)
+ );
+ }
+ }
+ else if (RD_FLD(instr, INSTR_OP2)==OP2_FB)
+ {
+ // cond, A, disp22
+ printf("%s%s %08X", fcond_names[RD_FLD(instr, INSTR_COND_H)],
+ RD_FLD(instr, INSTR_A) ? ",a" : "",
+ RD_FLD(instr, INSTR_DISP22));
+ }
+ else{
+ printf("Unknown:OP=0b00 OP2 = 0x%04X", RD_FLD(instr, INSTR_OP2));
+ assert(0);
+ }
}
-void sparc_printalu(char * basename , unsigned instr)
+void sparc_printalu(char * basename , unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
{
- // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13}
- if (RD_FLD(instr, INSTR_I)==0) {
- printf("%s r%d <- r%d ,r%d",basename, RD_FLD(instr, INSTR_RD),
- RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2));
- } else {
- printf("%s r%d <- r%d ,%d",basename, RD_FLD(instr, INSTR_RD),
- RD_FLD(instr, INSTR_RS1),
- SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
- }
+ // OP=OP_2 : RD, OP3, RS1: {I=0 -> RS2 I=1->SIMM13}
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ if (!labels)
+ printf("%s r%d <- r%d ,r%d",basename, RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2));
+ else
+ printf("%s l%d <- l%d ,l%d",basename, labelrd,labelrs1, labelrs2);
+ }
+ else
+ {
+ if (!labels)
+ printf("%s r%d <- r%d ,%d",basename, RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ else
+ printf("%s l%d <- l%d ,%d",basename, labelrd,labelrs1, SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
}
-void sparc_printshf(char * basename, unsigned instr)
+void sparc_printshf(char * basename, unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
{
- // OP=OP_2: RD, OP_3 RS1:
- // {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }}
- if (RD_FLD(instr, INSTR_I)==0) {
- printf("%s%d r%d <- r%d, by r%d ", (RD_FLD(instr, INSTR_X)==0 ? 32 : 64),
- basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),
- RD_FLD(instr, INSTR_RS2));
- } else {
- printf("%s%d r%d <- r%d, by 0x%04X ", basename,
- (RD_FLD(instr, INSTR_X)==0 ? 32 : 64),
- RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1),
- (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32)
- : RD_FLD(instr, INSTR_SHCNT64)) );
- }
+ //OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }}
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ if (!labels)
+ printf("%s%d r%d <- r%d, by r%d ",(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2));
+ else
+ printf("%s%d l%d <- l%d, by l%d ",(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), basename, labelrd, labelrs1, labelrs2);
+ }
+ else
+ {
+ if (!labels)
+ printf("%s%d r%d <- r%d, by 0x%04X ", basename,(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32) : RD_FLD(instr, INSTR_SHCNT64)) );
+ else
+ printf("%s%d l%d <- l%d, by 0x%04X ", basename,(RD_FLD(instr, INSTR_X)==0 ? 32 : 64), labelrd, labelrs1, (RD_FLD(instr, INSTR_X)==0 ? RD_FLD(instr, INSTR_SHCNT32) : RD_FLD(instr, INSTR_SHCNT64)) );
+ }
+
}
// Op2 class instructions
-void sparc_printfpu(unsigned instr)
+void sparc_printfpu(unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
{
- switch(RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON)
- {
- case OPF_FADDn:
- printf("FADDn");
- return;
- case OPF_FSUBn:
- printf("FSUBn");
- return;
- case OPF_FMOVn:
- printf("FMOVn");
- return;
- case OPF_FNEGn:
- printf("FNEGn");
- return;
- case OPF_FABSn:
- printf("FABSn");
- return;
- case OPF_FMULn:
- printf("FMULn");
- return;
- case OPF_FDIVn:
- printf("FDIVn");
- return;
- case OPF_FSQRTn:
- printf("FSQRTn");
- return;
- }
- switch (RD_FLD(instr, INSTR_OPF) &~OPF_MASK_TO)
- {
- case OPF_FxTOt:
- printf("FxTOt");
- return;
- case OPF_FiTOt:
- printf("FiTOt");
- return;
- }
-
- switch(RD_FLD(instr, INSTR_OPF))
- {
- case OPF_FsTOx:
- printf("OPF_FsTOx");
- return;
- case OPF_FsTOi:
- printf("OPF_FsTOi");
- return;
- case OPF_FsTOd:
- printf("OPF_FsTOd");
- return;
- case OPF_FsTOq:
- printf("OPF_FsTOq");
- return;
- case OPF_FdTOx:
- printf("OPF_FdTOx");
- return;
- case OPF_FdTOi:
- printf("OPF_FdTOi");
- return;
- case OPF_FqTOx:
- printf("OPF_FqTOx");
- return;
- case OPF_FdTOs:
- printf("OPF_FdTOs");
- return;
- case OPF_FdTOq:
- printf("OPF_FdTOq");
- return;
- case OPF_FqTOi:
- printf("OPF_FqTOi");
- return;
- case OPF_FqTOs:
- printf("OPF_FqTOs");
- return;
- case OPF_FqTOd:
- printf("OPF_FqTOd");
- return;
- case OPF_FsMULd:
- printf("OPF_FsMULd");
- return;
- case OPF_FdMULq:
- printf("OPF_FdMULq");
- return;
- }
+ switch(RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON)
+ {
+ case OPF_FADDn:
+ printf("FADDn");
+ return;
+ case OPF_FSUBn:
+ printf("FSUBn");
+ return;
+ case OPF_FMOVn:
+ printf("FMOVn");
+ return;
+ case OPF_FNEGn:
+ printf("FNEGn");
+ return;
+ case OPF_FABSn:
+ printf("FABSn");
+ return;
+ case OPF_FMULn:
+ printf("FMULn");
+ return;
+ case OPF_FDIVn:
+ printf("FDIVn");
+ return;
+ case OPF_FSQRTn:
+ printf("FSQRTn");
+ return;
+ }
+ switch (RD_FLD(instr, INSTR_OPF) &~OPF_MASK_TO)
+ {
+ case OPF_FxTOt:
+ printf("FxTOt");
+ return;
+ case OPF_FiTOt:
+ printf("FiTOt");
+ return;
+ }
+
+ switch(RD_FLD(instr, INSTR_OPF))
+ {
+ case OPF_FsTOx:
+ printf("OPF_FsTOx");
+ return;
+ case OPF_FsTOi:
+ printf("OPF_FsTOi");
+ return;
+ case OPF_FsTOd:
+ printf("OPF_FsTOd");
+ return;
+ case OPF_FsTOq:
+ printf("OPF_FsTOq");
+ return;
+ case OPF_FdTOx:
+ printf("OPF_FdTOx");
+ return;
+ case OPF_FdTOi:
+ printf("OPF_FdTOi");
+ return;
+ case OPF_FqTOx:
+ printf("OPF_FqTOx");
+ return;
+ case OPF_FdTOs:
+ printf("OPF_FdTOs");
+ return;
+ case OPF_FdTOq:
+ printf("OPF_FdTOq");
+ return;
+ case OPF_FqTOi:
+ printf("OPF_FqTOi");
+ return;
+ case OPF_FqTOs:
+ printf("OPF_FqTOs");
+ return;
+ case OPF_FqTOd:
+ printf("OPF_FqTOd");
+ return;
+ case OPF_FsMULd:
+ printf("OPF_FsMULd");
+ return;
+ case OPF_FdMULq:
+ printf("OPF_FdMULq");
+ return;
+ }
+
+ assert(0); // we don't know the FPU instruction yet
}
-void sparc_print2(unsigned instr)
+void sparc_print2(unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
{
- switch(RD_FLD(instr, INSTR_OP3))
- {
- case OP3_ADD:
- sparc_printalu("ADD", instr);
- return;
-
- case OP3_ADDcc:
- sparc_printalu("ADDcc", instr);
- return;
-
- case OP3_ADDC:
- sparc_printalu("ADDC", instr);
- return;
-
- case OP3_ADDCcc:
- sparc_printalu("ADDCcc", instr);
- return;
-
- case OP3_AND:
- sparc_printalu("AND", instr);
- return;
-
- case OP3_ANDcc:
- sparc_printalu("ANDcc", instr);
- return;
-
- case OP3_OR:
- sparc_printalu("OR", instr);
- return;
-
- case OP3_ORcc:
- sparc_printalu("ORcc", instr);
- return;
-
- case OP3_XOR:
- sparc_printalu("XOR", instr);
- return;
-
- case OP3_XORcc:
- sparc_printalu("XORcc", instr);
- return;
-
- case OP3_SUB:
- sparc_printalu("SUB", instr);
- return;
-
- case OP3_SUBcc:
- sparc_printalu("SUBcc", instr);
- return;
-
- case OP3_ANDN:
- sparc_printalu("ANDN", instr);
- return;
-
- case OP3_ANDNcc:
- sparc_printalu("ANDNcc", instr);
- return;
-
- case OP3_ORN:
- sparc_printalu("ORN", instr);
- return;
-
- case OP3_ORNcc:
- sparc_printalu("ORNcc", instr);
- return;
-
- case OP3_XNOR:
- sparc_printalu("XNOR", instr);
- return;
-
- case OP3_XNORcc:
- sparc_printalu("XNORcc", instr);
- return;
-
- case OP3_SUBC:
- sparc_printalu("SUBC", instr);
- return;
-
- case OP3_SUBCcc:
- sparc_printalu("SUBCcc", instr);
- return;
-
- case OP3_MULX:
- sparc_printalu("MULX", instr);
- return;
-
- case OP3_SDIVX:
- sparc_printalu("SDIVX", instr);
- return;
-
- case OP3_UDIVX:
- sparc_printalu("UDIVX", instr);
- return;
-
- case OP3_SLL:
- sparc_printshf("SLL",instr);
- return;
- case OP3_SRL:
- sparc_printshf("SRL",instr);
- return;
- case OP3_SRA:
- sparc_printshf("SRA",instr);
- return;
-
- case OP3_DONERETRY:
+ switch(RD_FLD(instr, INSTR_OP3))
+ {
+
+ case OP3_MOVcc:
{
- if (RD_FLD(instr, INSTR_FCN)==FCN_DONE)
- printf("DONE");
- else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY)
- printf("RETRY");
- else
- printf("DOH!");
- return;
- }
+ if (RD_FLD(instr, INSTR_I)==0)
+ printf("mov%s(%s) r%d <- r%d", icond_names[RD_FLD(instr, INSTR_COND_L)],
+ cc_names[(RD_FLD(instr, INSTR_CC2) << 2) | (RD_FLD(instr, INSTR_MOV_CC1) << 1) | RD_FLD(instr, INSTR_MOV_CC0)],
+ RD_FLD(instr, INSTR_RD),
+ RD_FLD(instr, INSTR_RS2));
+ else
+ printf("mov%s(%s) r%d <- %d", icond_names[RD_FLD(instr, INSTR_COND_L)],
+ cc_names[(RD_FLD(instr, INSTR_CC2) << 2) | (RD_FLD(instr, INSTR_MOV_CC1) << 1) | RD_FLD(instr, INSTR_MOV_CC0)],
+ RD_FLD(instr, INSTR_RD),
+ SIGN_EXTEND(RD_FLD(instr, INSTR_SIMM11),11));
+ return;
+ }
+
+
+ case OP3_ADD:
+ sparc_printalu("ADD", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ADDcc:
+ sparc_printalu("ADDcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ADDC:
+ sparc_printalu("ADDC", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ADDCcc:
+ sparc_printalu("ADDCcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_AND:
+ sparc_printalu("AND", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ANDcc:
+ sparc_printalu("ANDcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_OR:
+ sparc_printalu("OR", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ORcc:
+ sparc_printalu("ORcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XOR:
+ sparc_printalu("XOR", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XORcc:
+ sparc_printalu("XORcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUB:
+ sparc_printalu("SUB", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUBcc:
+ sparc_printalu("SUBcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ANDN:
+ sparc_printalu("ANDN", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ANDNcc:
+ sparc_printalu("ANDNcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ORN:
+ sparc_printalu("ORN", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_ORNcc:
+ sparc_printalu("ORNcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XNOR:
+ sparc_printalu("XNOR", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_XNORcc:
+ sparc_printalu("XNORcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUBC:
+ sparc_printalu("SUBC", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SUBCcc:
+ sparc_printalu("SUBCcc", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_MULX:
+ sparc_printalu("MULX", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SDIVX:
+ sparc_printalu("SDIVX", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_UDIVX:
+ sparc_printalu("UDIVX", instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_SLL:
+ sparc_printshf("SLL",instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_SRL:
+ sparc_printshf("SRL",instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_SRA:
+ sparc_printshf("SRA",instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_DONERETRY:
+ {
+ if (RD_FLD(instr, INSTR_FCN)==FCN_DONE)
+ printf("DONE");
+ else if (RD_FLD(instr, INSTR_FCN)==FCN_RETRY)
+ printf("RETRY");
+ return;
+ }
+
+ case OP3_FCMP:
+ {
+ unsigned fop_n =RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON;
+ if (fop_n==OPF_FCMPn)
+ printf("FCMP");
+ else if (fop_n==OPF_FCMPEn)
+ printf("FCMPE");
+ return;
+ }
+
+ case OP3_FPU:
+ sparc_printfpu(instr, labels, labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
+ printf("OP3_FLUSH");
+ return;
+ case OP3_FLUSHW: //OP=OP_2 I = 0
+ printf("OP3_FLUSHW");
+ return;
+ case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ if (!labels)
+ printf("JMPL link:r%d, to: r%d+r%d", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2) );
+ else
+ printf("JMPL link:l%d, to: l%d+l%d", labelrd,labelrs1,labelrs2 );
+ }
+ else
+ {
+ if (!labels)
+ printf("JMPL link:r%d, to: r%d+%d", RD_FLD(instr, INSTR_RD),RD_FLD(instr, INSTR_RS1),SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) );
+ else
+ printf("JMPL link:l%d, to: l%d+%d", labelrd,labelrs1,SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) );
+ }
+ return;
+
+ case OP3_POPC:
+ printf("POPC ????");
+ return;
+
+ case OP3_RETURN:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ {
+ if (!labels)
+ printf("RETURN r%d + r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2));
+ else
+ printf("RETURN l%d + l%d", labelrs1, labelrs2);
+ }
+ else
+ {
+ if (!labels)
+ printf("RETURN r%d + %d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ else
+ printf("RETURN l%d + %d", labelrs1, SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+ return;
+
+ case OP3_SAVE:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ {
+ if (!labels)
+ printf("save r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
+ else
+ printf("save l%d , l%d, l%d", labelrs1, labelrs2, labelrd);
+ }
+ else
+ {
+ if (!labels)
+ printf("save r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), RD_FLD(instr, INSTR_RD));
+ else
+ printf("save l%d , %d, l%d", labelrs1, SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), labelrd);
+ }
+ return;
+
+ case OP3_RESTORE:
+ if (RD_FLD(instr, INSTR_I) == 0)
+ {
+ if (!labels)
+ printf("RESTORE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
+ else
+ printf("RESTORE l%d , l%d, l%d", labelrs1, labelrs2, labelrd);
+ }
+ else
+ {
+ if (!labels)
+ printf("RESTORE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), RD_FLD(instr, INSTR_RD));
+ else
+ printf("RESTORE l04%d , %d, l04%d",labelrs1, SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)), labelrd);
+
+ }
+ return;
- case OP3_FCMP:
- {
- unsigned fop_n =RD_FLD(instr, INSTR_OPF) &~ OPF_MASK_ON;
- if (fop_n==OPF_FCMPn)
- printf("FCMP");
- else if (fop_n==OPF_FCMPEn)
- printf("FCMPE");
- else
- printf("DOH!");
- return;
- }
- case OP3_FPU:
- sparc_printfpu(instr);
- return;
-
- case OP3_FLUSH: //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
- printf("OP3_FLUSH");
- return;
- case OP3_FLUSHW: //OP=OP_2 I = 0
- printf("OP3_FLUSHW");
- return;
- case OP3_JMPL: //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
- if (RD_FLD(instr, INSTR_I)==0)
- printf("JMPL link:r%d, to: r%d+r%d", RD_FLD(instr, INSTR_RD),
- RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_RS2) );
- else
- printf("JMPL link:r%d, to: r%d+%d", RD_FLD(instr, INSTR_RD),
- RD_FLD(instr, INSTR_RS1),
- SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)) );
- return;
-
- case OP3_POPC:
- printf("POPC ????");
- return;
-
- case OP3_RETURN:
- if (RD_FLD(instr, INSTR_I) == 0)
- printf("RETURN r%d + r%d", RD_FLD(instr, INSTR_RS1),
- RD_FLD(instr, INSTR_RS2));
- else
- printf("RETURN r%d + %d", RD_FLD(instr, INSTR_RS1),
- SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
- return;
-
- case OP3_SAVE:
- if (RD_FLD(instr, INSTR_I) == 0)
- printf("save r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1),
- RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
- else
- printf("save r%d , %d, r%d", RD_FLD(instr, INSTR_RS1),
- SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)),
- RD_FLD(instr, INSTR_RD));
- return;
-
- case OP3_RESTORE:
- if (RD_FLD(instr, INSTR_I) == 0)
- printf("RESTORE r%d , r%d, r%d", RD_FLD(instr, INSTR_RS1),
- RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
- else
- printf("RESTORE r%d , %d, r%d", RD_FLD(instr, INSTR_RS1),
- SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)),
- RD_FLD(instr, INSTR_RD));
- return;
+ }
+ printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3));
+ assert(0);
+}
- }
+void sparc_printldst(char * basename, unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd , int labelccf)
+{
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ if (!labels)
+ printf("%s r%d <- r%d , r%d", basename,RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2));
+ else
+ printf("%s l04%d <- l%d , l%d", basename, labelrd, labelrs1, labelrs2);
+ }
+ else
+ {
+ if (!labels)
+ printf("%s r%d <- r%d , %d",basename, RD_FLD(instr, INSTR_RD), RD_FLD(instr, INSTR_RS1), SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ else
+ printf("%s l%d <- l%d, l%d", basename, labelrd, labelrs1,SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
+ }
+}
+void sparc_print3(unsigned instr, bool labels, int labelrs1, int labelrs2, int labelrd, int labelccf)
+{
+//#define OP3_LDFA 0b110000 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+//#define OP3_LDDFA 0b110011 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+//#define OP3_LDQFA 0b110010 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+//#define OP3_LDSTUB 0b001101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+//#define OP3_LDSTUBA 0b011101 //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
+ switch(RD_FLD(instr, INSTR_OP3))
+ {
+ //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+ case OP3_LDSTUB:
+ sparc_printldst("LDSTUB", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STB:
+ sparc_printldst("STB", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STH:
+ sparc_printldst("STH", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STW:
+ sparc_printldst("STW", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_STX:
+ sparc_printldst("STX", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDSB:
+ sparc_printldst("LDSB", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDSH:
+ sparc_printldst("LDSH", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDSW:
+ sparc_printldst("LDSW", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDUB:
+ sparc_printldst("LDUB", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDUH:
+ sparc_printldst("LDUH", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDUW:
+ sparc_printldst("LDUW", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_LDX:
+ sparc_printldst("LDX", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_CASA:
+ if (RD_FLD(instr, INSTR_I)==0)
+ {
+ if (!labels)
+ printf("CASA [r%d] %%%d, r%d, r%d", RD_FLD(instr, INSTR_RS1),RD_FLD(instr, INSTR_IMMASI), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
+ else
+ printf("CASA [l%d] %%%d, l%d, l%d", labelrs1,RD_FLD(instr, INSTR_IMMASI), labelrs2, labelrd);
+ }
+ else
+ {
+ if (!labels)
+ printf("CASA [r%d] , r%d, r%d", RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
+ else
+ printf("CASA [l%d] , l%d, l%d", labelrs1, labelrs2, labelrd);
+ }
+
+ sparc_printalu("CASA", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+
+ return;
+
+ case OP3_CASXA:
+ sparc_printalu("CASXA", instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_STFA:
+ sparc_printalu("STFA",instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_STDFA:
+ sparc_printalu("STDFA",instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+ case OP3_STQFA:
+ sparc_printalu("STQFA",instr,labels,labelrs1, labelrs2, labelrd, labelccf);
+ return;
+
+ case OP3_PREFETCH:
+ printf("PREFETCH ??? ");
+ return;
+
+ case OP3_PREFETCHA:
+ printf("PREFETCHA ??? ");
+ return;
+ }
- printf("Unknown:OP=0b10 OP3 = 0x%04X", RD_FLD(instr, INSTR_OP3));
+ printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3));
+ assert(0);
}
-void sparc_printldst(char * basename, unsigned instr)
-{
- if (RD_FLD(instr, INSTR_I)==0)
- printf("%s r%d <- r%d , r%d", basename, RD_FLD(instr, INSTR_RD),
- RD_FLD(instr, INSTR_RS1), RD_FLD(instr, INSTR_RS2));
- else
- printf("%s r%d <- r%d , %d",basename, RD_FLD(instr, INSTR_RD),
- RD_FLD(instr, INSTR_RS1),
- SIGN_EXTEND13(RD_FLD(instr, INSTR_SIMM13)));
-}
-void sparc_print3(unsigned instr)
-{
- //#define OP3_LDFA 0b110000
- //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-
- //#define OP3_LDDFA 0b110011
- //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-
- //#define OP3_LDQFA 0b110010
- //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-
- //#define OP3_LDSTUB 0b001101
- //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
-
- //#define OP3_LDSTUBA 0b011101
- //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
-
- switch(RD_FLD(instr, INSTR_OP3))
- {
- //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
- case OP3_LDSTUB:
- sparc_printldst("LDSTUB", instr);
- return;
-
- case OP3_STB:
- sparc_printldst("STB", instr);
- return;
-
- case OP3_STH:
- sparc_printldst("STH", instr);
- return;
-
- case OP3_STW:
- sparc_printldst("STW", instr);
- return;
-
- case OP3_STX:
- sparc_printldst("STX", instr);
- return;
-
- case OP3_LDSB:
- sparc_printldst("LDSB", instr);
- return;
-
- case OP3_LDSH:
- sparc_printldst("LDSH", instr);
- return;
-
- case OP3_LDSW:
- sparc_printldst("LDSW", instr);
- return;
-
- case OP3_LDUB:
- sparc_printldst("LDUB", instr);
- return;
-
- case OP3_LDUH:
- sparc_printldst("LDUH", instr);
- return;
-
- case OP3_LDUW:
- sparc_printldst("LDUW", instr);
- return;
-
- case OP3_LDX:
- sparc_printldst("LDX", instr);
- return;
-
- case OP3_CASA:
- if (RD_FLD(instr, INSTR_I)==0)
- printf("CASA [r%d] %%%d, r%d, r%d", RD_FLD(instr, INSTR_RS1),
- RD_FLD(instr, INSTR_IMMASI), RD_FLD(instr, INSTR_RS2),
- RD_FLD(instr, INSTR_RD));
- else
- printf("CASA [r%d] , r%d, r%d", RD_FLD(instr, INSTR_RS1),
- RD_FLD(instr, INSTR_RS2), RD_FLD(instr, INSTR_RD));
-
- sparc_printalu("CASA", instr);
-
- return;
-
- case OP3_CASXA:
- sparc_printalu("CASXA", instr);
- return;
- case OP3_STFA:
- sparc_printalu("STFA",instr);
- return;
- case OP3_STDFA:
- sparc_printalu("STDFA",instr);
- return;
- case OP3_STQFA:
- sparc_printalu("STQFA",instr);
- return;
-
- case OP3_PREFETCH:
- printf("PREFETCH ??? ");
- return;
-
- case OP3_PREFETCHA:
- printf("PREFETCHA ??? ");
- return;
- }
- printf("Unknown OP_3: OP3 = %08X", RD_FLD(instr, INSTR_OP3));
+void sparc_print_pseudo(unsigned instr, int labelrs1, int labelrs2, int labelrd, int labelccf)
+{
+ if (RD_FLD(instr,INSTR_OP)==OP_CALL)
+ printf("CALL disp:+%08X", instr & 0x3FFFFFFF);
+ else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+ sparc_printbr(instr,true,labelrs1, labelrs2, labelrd, labelccf);
+ else if (RD_FLD(instr,INSTR_OP)==OP_2)
+ sparc_print2(instr,true,labelrs1, labelrs2, labelrd, labelccf);
+ else if (RD_FLD(instr,INSTR_OP)==OP_3)
+ sparc_print3(instr,true,labelrs1, labelrs2, labelrd, labelccf);
}
void sparc_print(unsigned instr)
{
- printf("(%08X) ", instr);
- if (RD_FLD(instr,INSTR_OP)==OP_CALL)
- printf("CALL disp:+%08X", instr & 0x3FFFFFFF);
- else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
- sparc_printbr(instr);
- else if (RD_FLD(instr,INSTR_OP)==OP_2)
- sparc_print2(instr);
- else if (RD_FLD(instr,INSTR_OP)==OP_3)
- sparc_print3(instr);
+ if (RD_FLD(instr,INSTR_OP)==OP_CALL)
+ printf("CALL disp:+%08X", instr & 0x3FFFFFFF);
+ else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+ sparc_printbr(instr,false,0, 0, 0, 0);
+ else if (RD_FLD(instr,INSTR_OP)==OP_2)
+ sparc_print2(instr,false,0, 0, 0, 0);
+ else if (RD_FLD(instr,INSTR_OP)==OP_3)
+ sparc_print3(instr,false,0, 0, 0, 0 );
}
Index: llvm/lib/Reoptimizer/BinInterface/sparcdis.h
diff -u llvm/lib/Reoptimizer/BinInterface/sparcdis.h:1.2 llvm/lib/Reoptimizer/BinInterface/sparcdis.h:1.3
--- llvm/lib/Reoptimizer/BinInterface/sparcdis.h:1.2 Wed Nov 13 14:17:52 2002
+++ llvm/lib/Reoptimizer/BinInterface/sparcdis.h Wed Nov 27 20:20:42 2002
@@ -1 +1,34 @@
-void sparc_print(unsigned instr);
+//*****************************************************************************
+// SPARC Instruction Disassembler
+//
+// Disassembler API Header
+//
+// * Initial implementation
+// * Added support for MOVcc (somehow I missed it?!)
+// * Added support for pseudo-disassembly
+// ( In the print routine for bin-interface we want
+// to be able to print the internal SSA form with
+// labels instead of registers. And we wish to
+// ommit RD from the view when we are not explicitly
+// reading from it)
+//
+// Todo:
+// * On the instructions that don't read from RD
+// do not print the label field (we get l-1 when we print)
+//
+// 2002 Cameron Buschardt
+//*****************************************************************************
+
+#ifndef __SPARCDIS__
+#define __SPARCDIS__
+// Conventional Disassembly. Prints instruction (no newline)
+void sparc_print(unsigned instr);
+
+// Pseudo disasm
+// uses the integers in labelrs1, labelrs2, labelrd, and labelccf as
+// gen labels for the parameter sources
+// instead of printing rxx for rs1, it will print l__labelrs1__
+void sparc_print_pseudo(unsigned instr, int labelrs1, int labelrs2, int labelrd, int labelccf);
+
+
+#endif
\ No newline at end of file
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