[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/analyze.cpp fvector.h sparc9.h
Misha Brukman
brukman at neo.cs.uiuc.edu
Mon Nov 18 16:36:01 PST 2002
Changes in directory llvm/lib/Reoptimizer/BinInterface:
analyze.cpp updated: 1.2 -> 1.3
fvector.h updated: 1.1 -> 1.2
sparc9.h updated: 1.4 -> 1.5
---
Log message:
* analyze.cpp - added some comments
* fvector.h - added newline at end of file (gcc sometimes complains)
* sparc9.h - now triple-checked (pre-processed using binproc and checked
entries, they are correct), returned binary formatting to
original (no spaces between each group of 4 digits)
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/BinInterface/analyze.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.2 llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.3
--- llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.2 Tue Nov 12 20:44:48 2002
+++ llvm/lib/Reoptimizer/BinInterface/analyze.cpp Mon Nov 18 16:39:11 2002
@@ -171,6 +171,7 @@
return 0;
}
+// returns which register is written to
unsigned sparc_getwrites(unsigned mask, unsigned instr)
{
if (mask & IF_RD)
@@ -179,6 +180,7 @@
return 0;
}
+// returns which registers are read
unsigned sparc_getreads (unsigned mask, unsigned instr)
{
unsigned m = 0;
Index: llvm/lib/Reoptimizer/BinInterface/fvector.h
diff -u llvm/lib/Reoptimizer/BinInterface/fvector.h:1.1 llvm/lib/Reoptimizer/BinInterface/fvector.h:1.2
--- llvm/lib/Reoptimizer/BinInterface/fvector.h:1.1 Fri Nov 8 04:38:13 2002
+++ llvm/lib/Reoptimizer/BinInterface/fvector.h Mon Nov 18 16:39:11 2002
@@ -83,4 +83,4 @@
};
-#endif
\ No newline at end of file
+#endif
Index: llvm/lib/Reoptimizer/BinInterface/sparc9.h
diff -u llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.4 llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.5
--- llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.4 Tue Nov 12 20:40:00 2002
+++ llvm/lib/Reoptimizer/BinInterface/sparc9.h Mon Nov 18 16:39:11 2002
@@ -177,48 +177,48 @@
// SIMM13
//**********************************
-#define OP3_ADD 0x0 // 0b00 0000
-#define OP3_ADDC 0x8 // 0b00 1000
-#define OP3_AND 0x1 // 0b00 0001
-#define OP3_OR 0x2 // 0b00 0010
-#define OP3_XOR 0x3 // 0b00 0011
-#define OP3_SUB 0x4 // 0b00 0100
-#define OP3_ANDN 0x5 // 0b00 0101
-#define OP3_ORN 0x6 // 0b00 0110
-#define OP3_XNOR 0x7 // 0b00 0111
-#define OP3_SUBC 0xc // 0b00 1100
-#define OP3_ADDcc 0x10 // 0b01 0000
-#define OP3_ADDCcc 0x18 // 0b01 1000
-#define OP3_ANDcc 0x11 // 0b01 0001
-#define OP3_ORcc 0x12 // 0b01 0010
-#define OP3_XORcc 0x13 // 0b01 0011
-#define OP3_SUBcc 0x14 // 0b01 0100
-#define OP3_ANDNcc 0x15 // 0b01 0101
-#define OP3_ORNcc 0x16 // 0b01 0110
-#define OP3_XNORcc 0x17 // 0b01 0111
-#define OP3_SUBCcc 0x1c // 0b01 1100
-#define OP3_MULX 0x9 // 0b00 1001
-#define OP3_SDIVX 0x2d // 0b10 1101
-#define OP3_UDIVX 0xd // 0b00 1101
+#define OP3_ADD 0x0 // 0b000000
+#define OP3_ADDC 0x8 // 0b001000
+#define OP3_AND 0x1 // 0b000001
+#define OP3_OR 0x2 // 0b000010
+#define OP3_XOR 0x3 // 0b000011
+#define OP3_SUB 0x4 // 0b000100
+#define OP3_ANDN 0x5 // 0b000101
+#define OP3_ORN 0x6 // 0b000110
+#define OP3_XNOR 0x7 // 0b000111
+#define OP3_SUBC 0xc // 0b001100
+#define OP3_ADDcc 0x10 // 0b010000
+#define OP3_ADDCcc 0x18 // 0b011000
+#define OP3_ANDcc 0x11 // 0b010001
+#define OP3_ORcc 0x12 // 0b010010
+#define OP3_XORcc 0x13 // 0b010011
+#define OP3_SUBcc 0x14 // 0b010100
+#define OP3_ANDNcc 0x15 // 0b010101
+#define OP3_ORNcc 0x16 // 0b010110
+#define OP3_XNORcc 0x17 // 0b010111
+#define OP3_SUBCcc 0x1c // 0b011100
+#define OP3_MULX 0x9 // 0b001001
+#define OP3_SDIVX 0x2d // 0b101101
+#define OP3_UDIVX 0xd // 0b001101
//Op3 members
-#define OP3_CASA 0x3c // 0b11 1100
-#define OP3_CASXA 0x3e // 0b11 1110
+#define OP3_CASA 0x3c // 0b111100
+#define OP3_CASXA 0x3e // 0b111110
//Instructions below generated with:
//OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }}
-#define OP3_SLL 0x25 // 0b10 0101
-#define OP3_SRL 0x26 // 0b10 0110
-#define OP3_SRA 0x27 // 0b10 0111
+#define OP3_SLL 0x25 // 0b100101
+#define OP3_SRL 0x26 // 0b100110
+#define OP3_SRA 0x27 // 0b100111
// class OP_3
-#define OP3_STFA 0x34 // 0b11 0100
-#define OP3_STDFA 0x37 // 0b11 0111
-#define OP3_STQFA 0x36 // 0b11 0110
+#define OP3_STFA 0x34 // 0b110100
+#define OP3_STDFA 0x37 // 0b110111
+#define OP3_STQFA 0x36 // 0b110110
//Instructions below generated with:
//OP=OP_2: FCN
-#define OP3_DONERETRY 0x3e // 0b11 1110
+#define OP3_DONERETRY 0x3e // 0b111110
#define FCN_DONE 0
#define FCN_RETRY 1
@@ -235,82 +235,82 @@
//Instructions below generated with
//OP=OP_2: CC1_H, CC0_H, RS1, OPF, RS2
-#define OP3_FCMP 0x35 // 0b 11 0101
-#define OPF_FCMPn 0x50 // 0b0 0101 0000
-#define OPF_FCMPEn 0x54 // 0b0 0101 0100
+#define OP3_FCMP 0x35 // 0b110101
+#define OPF_FCMPn 0x50 // 0b001010000
+#define OPF_FCMPEn 0x54 // 0b001010100
//Instructions below generated with
//OP=OP_2: RD, OP3 RS1, OPF, RS2
-#define OP3_FPU 0x34 // 0b 11 0100
-#define OPF_FADDn 0x40 // 0b0 0100 0000
-#define OPF_FSUBn 0x44 // 0b0 0100 0100
-#define OPF_FMOVn 0x0 // 0b0 0000 0000
-#define OPF_FNEGn 0x4 // 0b0 0000 0100
-#define OPF_FABSn 0x8 // 0b0 0000 1000
-#define OPF_FMULn 0x48 // 0b0 0100 1000
-#define OPF_FDIVn 0x4c // 0b0 0100 1100
-#define OPF_FSQRTn 0x28 // 0b0 0010 1000
-#define OPF_FsTOx 0x81 // 0b0 1000 0001
-#define OPF_FsTOi 0xd1 // 0b0 1101 0001
-#define OPF_FsTOd 0xc9 // 0b0 1100 1001
-#define OPF_FsTOq 0xcd // 0b0 1100 1101
-#define OPF_FdTOx 0x82 // 0b0 1000 0010
-#define OPF_FdTOi 0xd2 // 0b0 1101 0010
-#define OPF_FdTOs 0xc6 // 0b0 1100 0110
-#define OPF_FdTOq 0xce // 0b0 1100 1110
-#define OPF_FqTOx 0x83 // 0b0 1000 0011
-#define OPF_FqTOi 0xd3 // 0b0 1101 0011
-#define OPF_FqTOs 0xc7 // 0b0 1100 0111
-#define OPF_FqTOd 0xcb // 0b0 1100 1011
-#define OPF_FxTOt 0x80 // 0b0 1000 0000
-#define OPF_FiTOt 0xc0 // 0b0 1100 0000
-#define OPF_FsMULd 0x69 // 0b0 0110 1001
-#define OPF_FdMULq 0x6e // 0b0 0110 1110
-
-
-#define OP3_FLUSH 0x3b // 0b11 1011 //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
-#define OP3_FLUSHW 0x2b // 0b10 1011 //OP=OP_2 I = 0
-#define OP3_JMPL 0x38 // 0b11 1000 //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
+#define OP3_FPU 0x34 // 0b110100
+#define OPF_FADDn 0x40 // 0b001000000
+#define OPF_FSUBn 0x44 // 0b001000100
+#define OPF_FMOVn 0x0 // 0b000000000
+#define OPF_FNEGn 0x4 // 0b000000100
+#define OPF_FABSn 0x8 // 0b000001000
+#define OPF_FMULn 0x48 // 0b001001000
+#define OPF_FDIVn 0x4c // 0b001001100
+#define OPF_FSQRTn 0x28 // 0b000101000
+#define OPF_FsTOx 0x81 // 0b010000001
+#define OPF_FsTOi 0xd1 // 0b011010001
+#define OPF_FsTOd 0xc9 // 0b011001001
+#define OPF_FsTOq 0xcd // 0b011001101
+#define OPF_FdTOx 0x82 // 0b010000010
+#define OPF_FdTOi 0xd2 // 0b011010010
+#define OPF_FdTOs 0xc6 // 0b011000110
+#define OPF_FdTOq 0xce // 0b011001110
+#define OPF_FqTOx 0x83 // 0b010000011
+#define OPF_FqTOi 0xd3 // 0b011010011
+#define OPF_FqTOs 0xc7 // 0b011000111
+#define OPF_FqTOd 0xcb // 0b011001011
+#define OPF_FxTOt 0x80 // 0b010000000
+#define OPF_FiTOt 0xc0 // 0b011000000
+#define OPF_FsMULd 0x69 // 0b001101001
+#define OPF_FdMULq 0x6e // 0b001101110
+
+
+#define OP3_FLUSH 0x3b // 0b111011 //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
+#define OP3_FLUSHW 0x2b // 0b101011 //OP=OP_2 I = 0
+#define OP3_JMPL 0x38 // 0b111000 //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDFA 0x30 // 0b11 0000
+#define OP3_LDFA 0x30 // 0b110000
//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDDFA 0x33 // 0b11 0011
+#define OP3_LDDFA 0x33 // 0b110011
//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDQFA 0x32 // 0b11 0010
+#define OP3_LDQFA 0x32 // 0b110010
-#define OP3_LDSTUB 0xd // 0b00 1101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
-#define OP3_STB 0x5 // 0b00 0101
-#define OP3_STH 0x6 // 0b00 0110
-#define OP3_STW 0x4 // 0b00 0100
-#define OP3_STX 0x7 // 0b00 0111
-#define OP3_LDSB 0x9 // 0b00 1001
-#define OP3_LDSH 0xa // 0b00 1010
-#define OP3_LDSW 0x8 // 0b00 1000
-#define OP3_LDUB 0x1 // 0b00 0001
-#define OP3_LDUH 0x2 // 0b00 0010
-#define OP3_LDUW 0x0 // 0b00 0000
-#define OP3_LDX 0xb // 0b00 1011
+#define OP3_LDSTUB 0xd // 0b001101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+#define OP3_STB 0x5 // 0b000101
+#define OP3_STH 0x6 // 0b000110
+#define OP3_STW 0x4 // 0b000100
+#define OP3_STX 0x7 // 0b000111
+#define OP3_LDSB 0x9 // 0b001001
+#define OP3_LDSH 0xa // 0b001010
+#define OP3_LDSW 0x8 // 0b001000
+#define OP3_LDUB 0x1 // 0b000001
+#define OP3_LDUH 0x2 // 0b000010
+#define OP3_LDUW 0x0 // 0b000000
+#define OP3_LDX 0xb // 0b001011
//OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
-#define OP3_LDSTUBA 0x1d // 0b01 1101
+#define OP3_LDSTUBA 0x1d // 0b011101
//OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set
-#define OP3_MEMBAR 0x28 // 0b10 1000
+#define OP3_MEMBAR 0x28 // 0b101000
//These two instructions are FUNKY as hell
-#define OP3_FMOVcc 0x35 // 0b11 0101 //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
-#define OP3_MOVcc 0x2c // 0b10 1100 //
+#define OP3_FMOVcc 0x35 // 0b110101 //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
+#define OP3_MOVcc 0x2c // 0b101100 //
-#define OP3_POPC 0x2e // 0b10 1110
-#define OP3_PREFETCH 0x2d // 0b10 1101
-#define OP3_PREFETCHA 0x3d // 0b11 1101
-#define OP3_RETURN 0x39 // 0b11 1001
-#define OP3_SAVE 0x3c // 0b11 1100
-#define OP3_RESTORE 0x3d // 0b11 1101
+#define OP3_POPC 0x2e // 0b101110
+#define OP3_PREFETCH 0x2d // 0b101101
+#define OP3_PREFETCHA 0x3d // 0b111101
+#define OP3_RETURN 0x39 // 0b111001
+#define OP3_SAVE 0x3c // 0b111100
+#define OP3_RESTORE 0x3d // 0b111101
-#define OP3_SAVDRESTD 0x31 // 0b11 0001
+#define OP3_SAVDRESTD 0x31 // 0b110001
#define FCN_SAVED 0
#define FCN_RESTORED 1
-#define OP3_TRAP 0x3a // 0b11 1010 //integer trap
+#define OP3_TRAP 0x3a // 0b111010 //integer trap
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