[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/analyze.cpp analyze.h

Misha Brukman brukman at neo.cs.uiuc.edu
Tue Nov 12 20:43:00 PST 2002


Changes in directory llvm/lib/Reoptimizer/BinInterface:

analyze.cpp updated: 1.1 -> 1.2
analyze.h updated: 1.1 -> 1.2

---
Log message:

* Tabs to spaces
* Got rid of ^M (Windows EOL)
* #include sparc9.h not .hp
* Wrap code at 80 chars per line
* Fixed comments at top of file


---
Diffs of the changes:

Index: llvm/lib/Reoptimizer/BinInterface/analyze.cpp
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.1 llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.2
--- llvm/lib/Reoptimizer/BinInterface/analyze.cpp:1.1	Fri Nov  8 04:38:12 2002
+++ llvm/lib/Reoptimizer/BinInterface/analyze.cpp	Tue Nov 12 20:44:48 2002
@@ -1,4 +1,4 @@
-//*****************************************************************************
+//===-----------------------------------------------------------*- C++ -*--===//
 //                          SPARC Instruction Analyzer
 //
 //  Implementation of Analysis API
@@ -6,195 +6,194 @@
 //  * Need to add support for register conditional branches
 //
 // 2002 Cameron Buschardt
-//*****************************************************************************
+//===----------------------------------------------------------------------===//
 
 #include <stdio.h>
 #include <stdlib.h>
-
-#include "sparc9.hp"	// include the preprocessed header
-#include "analyze.h"
 #include <assert.h>
+#include "sparc9.h"
+#include "analyze.h"
 
 unsigned sparc_analyzebr(unsigned instr)
 {
-	// look at the OP2 field
-	if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
-	{
-		if (RD_FLD(instr, INSTR_RD) == 0)
-			return 0;						// This is the special encoding for NOP
-		else
-			return IF_RD;
-	}
-	else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
-	{
-		return IF_RCC | IF_BR;
-	}
-	else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
-		return IF_RCC;
-	else{
-		printf("Unknown:OP=0b00 OP2 = 0x%04X\n", RD_FLD(instr, INSTR_OP2));
-		assert(0);
-		return 0;
-	}
+  // look at the OP2 field
+  if (RD_FLD(instr, INSTR_OP2)==OP2_SETHI)
+  {
+    if (RD_FLD(instr, INSTR_RD) == 0)
+      return 0;                       // This is the special encoding for NOP
+    else
+      return IF_RD;
+  }
+  else if (RD_FLD(instr, INSTR_OP2)==OP2_BICC)
+  {
+    return IF_RCC | IF_BR;
+  }
+  else if (RD_FLD(instr, INSTR_OP2)==OP2_BPR)
+    return IF_RCC;
+  else{
+    printf("Unknown:OP=0b00 OP2 = 0x%04X\n", RD_FLD(instr, INSTR_OP2));
+    assert(0);
+    return 0;
+  }
 }
 unsigned sparc_analyze_c2(unsigned instr)
 {
-	switch(RD_FLD(instr, INSTR_OP3))
-	{
-	case OP3_DONERETRY:
-		return 0;
-	
-	case OP3_FCMP:
-	case OP3_FPU:
-		assert(0);
-		return 0;
-
-	case OP3_FLUSHW:	//OP=OP_2 I = 0
-		return 0;
-
-	case OP3_FLUSH:		//OP=OP_2 RS1 {I=0 -> IF_RS2, I=1->simm13}
-		if (RD_FLD(instr, INSTR_I) == 0)
-			return IF_RS1 | IF_RS2;
-		else
-			return IF_RS1;
-
-	case OP3_JMPL:		//OP=OP_2 RD, IF_RS1 {I=0-> IF_RS2, I=1->SIMM13}
-	case OP3_ADD:
-	case OP3_AND:
-	case OP3_OR:
-	case OP3_XOR:
-	case OP3_SUB:
-	case OP3_ANDN:
-	case OP3_ORN:
-	case OP3_XNOR:
-	case OP3_MULX:
-	case OP3_SDIVX:
-	case OP3_UDIVX:
-	case OP3_SLL:
-	case OP3_SRL:
-	case OP3_SRA:
-	case OP3_SAVE:		
-	case OP3_RETURN:	
-	case OP3_RESTORE:	
-		if (RD_FLD(instr, INSTR_I) == 0)
-			return IF_RD | IF_RS1 | IF_RS2;
-		else
-			return IF_RD | IF_RS1;
-
-	case OP3_ADDC:
-	case OP3_SUBC:
-		if (RD_FLD(instr, INSTR_I) == 0)
-			return IF_RD| IF_RS1 | IF_RS2 | IF_RCC;
-		else
-			return IF_RD| IF_RS1 | IF_RCC;
-
-
-
-	case OP3_XNORcc:
-	case OP3_ANDNcc:
-	case OP3_ANDcc:
-	case OP3_ADDcc:
-	case OP3_ORcc:
-	case OP3_ORNcc:
-	case OP3_SUBcc:
-	case OP3_XORcc:
-		if (RD_FLD(instr, INSTR_I) == 0)
-			return IF_RD | IF_RS1 | IF_RS2 | IF_WCC;
-		else
-			return IF_RD | IF_RS1 | IF_WCC;
-
-	case OP3_ADDCcc:
-	case OP3_SUBCcc:
-		if (RD_FLD(instr, INSTR_I) == 0)
-			return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC;
-		else
-			return IF_RD | IF_RS1 | IF_WCC | IF_RCC;
-		
-	default:
-		printf("Unknown:OP=0b10 OP3 = 0x%04X\n", RD_FLD(instr, INSTR_OP3));
-		assert(0);
-		
-	}
+  switch(RD_FLD(instr, INSTR_OP3))
+  {
+  case OP3_DONERETRY:
+    return 0;
+    
+  case OP3_FCMP:
+  case OP3_FPU:
+    assert(0);
+    return 0;
+
+  case OP3_FLUSHW:    //OP=OP_2 I = 0
+    return 0;
+
+  case OP3_FLUSH:     //OP=OP_2 RS1 {I=0 -> IF_RS2, I=1->simm13}
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RS1 | IF_RS2;
+    else
+      return IF_RS1;
+
+  case OP3_JMPL:      //OP=OP_2 RD, IF_RS1 {I=0-> IF_RS2, I=1->SIMM13}
+  case OP3_ADD:
+  case OP3_AND:
+  case OP3_OR:
+  case OP3_XOR:
+  case OP3_SUB:
+  case OP3_ANDN:
+  case OP3_ORN:
+  case OP3_XNOR:
+  case OP3_MULX:
+  case OP3_SDIVX:
+  case OP3_UDIVX:
+  case OP3_SLL:
+  case OP3_SRL:
+  case OP3_SRA:
+  case OP3_SAVE:      
+  case OP3_RETURN:    
+  case OP3_RESTORE:   
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RD | IF_RS1 | IF_RS2;
+    else
+      return IF_RD | IF_RS1;
+
+  case OP3_ADDC:
+  case OP3_SUBC:
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RD| IF_RS1 | IF_RS2 | IF_RCC;
+    else
+      return IF_RD| IF_RS1 | IF_RCC;
+
+
+
+  case OP3_XNORcc:
+  case OP3_ANDNcc:
+  case OP3_ANDcc:
+  case OP3_ADDcc:
+  case OP3_ORcc:
+  case OP3_ORNcc:
+  case OP3_SUBcc:
+  case OP3_XORcc:
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RD | IF_RS1 | IF_RS2 | IF_WCC;
+    else
+      return IF_RD | IF_RS1 | IF_WCC;
+
+  case OP3_ADDCcc:
+  case OP3_SUBCcc:
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RD | IF_RS1 | IF_RS2 | IF_WCC | IF_RCC;
+    else
+      return IF_RD | IF_RS1 | IF_WCC | IF_RCC;
+        
+  default:
+    printf("Unknown:OP=0b10 OP3 = 0x%04X\n", RD_FLD(instr, INSTR_OP3));
+    assert(0);
+        
+  }
 }
 
 
 unsigned sparc_analyze3(unsigned instr)
 {
-	switch(RD_FLD(instr, INSTR_OP3))
-	{
-		//OP=OP_3 RD, IF_RS1  {I=0->IF_RS2, I=1->SIMM13}
-		case OP3_STB:
-		case OP3_STH:
-		case OP3_STW:
-		case OP3_STX:
-		case OP3_LDSB:	
-		case OP3_LDSH:
-		case OP3_LDSW:
-		case OP3_LDUB:
-		case OP3_LDUH:	
-		case OP3_LDUW:
-		case OP3_LDX:
-		case OP3_LDSTUB:
-		case OP3_STFA:
-		case OP3_STDFA:
-		case OP3_STQFA:
-			if (RD_FLD(instr, INSTR_I) == 0)
-				return IF_RD | IF_RS1 | IF_RS2;
-			else
-				return IF_RD | IF_RS1;
-	
-		case OP3_CASXA:
-		case OP3_CASA:
-			return IF_RD | IF_RS1 | IF_RS2;
-			
-		case OP3_PREFETCHA:	
-		case OP3_PREFETCH:
-			if (RD_FLD(instr, INSTR_I) == 0)
-				return IF_RS1 | IF_RS2;
-			else
-				return IF_RS1;
-
-		default:
-			printf("Unknown OP_3: OP3 = %08X\n", RD_FLD(instr, INSTR_OP3));
-			assert(0);
-	}
+  switch(RD_FLD(instr, INSTR_OP3))
+  {
+    //OP=OP_3 RD, IF_RS1  {I=0->IF_RS2, I=1->SIMM13}
+  case OP3_STB:
+  case OP3_STH:
+  case OP3_STW:
+  case OP3_STX:
+  case OP3_LDSB:  
+  case OP3_LDSH:
+  case OP3_LDSW:
+  case OP3_LDUB:
+  case OP3_LDUH:  
+  case OP3_LDUW:
+  case OP3_LDX:
+  case OP3_LDSTUB:
+  case OP3_STFA:
+  case OP3_STDFA:
+  case OP3_STQFA:
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RD | IF_RS1 | IF_RS2;
+    else
+      return IF_RD | IF_RS1;
+    
+  case OP3_CASXA:
+  case OP3_CASA:
+    return IF_RD | IF_RS1 | IF_RS2;
+            
+  case OP3_PREFETCHA: 
+  case OP3_PREFETCH:
+    if (RD_FLD(instr, INSTR_I) == 0)
+      return IF_RS1 | IF_RS2;
+    else
+      return IF_RS1;
+
+  default:
+    printf("Unknown OP_3: OP3 = %08X\n", RD_FLD(instr, INSTR_OP3));
+    assert(0);
+  }
 }
 
 unsigned sparc_analyze(unsigned instr)
 {
-	if (RD_FLD(instr,INSTR_OP)==OP_2)
-		return sparc_analyze_c2(instr);
-	else if (RD_FLD(instr,INSTR_OP)==OP_3)
-		return sparc_analyze3(instr);
-	else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
-		return sparc_analyzebr(instr);
-	else
-		return 0;
+  if (RD_FLD(instr,INSTR_OP)==OP_2)
+    return sparc_analyze_c2(instr);
+  else if (RD_FLD(instr,INSTR_OP)==OP_3)
+    return sparc_analyze3(instr);
+  else if (RD_FLD(instr,INSTR_OP)==OP_BRANCH)
+    return sparc_analyzebr(instr);
+  else
+    return 0;
 }
 
 unsigned sparc_getwrites(unsigned mask, unsigned instr)
 {
-	if (mask & IF_RD)
-		return (1 << RD_FLD(instr, INSTR_RD));
-	else
-		return 0;
+  if (mask & IF_RD)
+    return (1 << RD_FLD(instr, INSTR_RD));
+  else
+    return 0;
 }
 
 unsigned sparc_getreads (unsigned mask, unsigned instr)
 {
-	unsigned m = 0;
-	
-	if (mask & IF_RS1)
-		m |= (1 << RD_FLD(instr, INSTR_RS1));
+  unsigned m = 0;
+    
+  if (mask & IF_RS1)
+    m |= (1 << RD_FLD(instr, INSTR_RS1));
 
-	if (mask & IF_RS2)
-		m |= (1 << RD_FLD(instr, INSTR_RS2));
+  if (mask & IF_RS2)
+    m |= (1 << RD_FLD(instr, INSTR_RS2));
 
-	return m;
+  return m;
 }
 
-unsigned sparc_getcc    (unsigned mask, unsigned instr) // bit 0 -> CC READ , bit 1 -> CC write
+// bit 0 -> CC READ , bit 1 -> CC write
+unsigned sparc_getcc (unsigned mask, unsigned instr)
 {
-	return (mask & (IF_WCC | IF_RCC));
+  return (mask & (IF_WCC | IF_RCC));
 }
-


Index: llvm/lib/Reoptimizer/BinInterface/analyze.h
diff -u llvm/lib/Reoptimizer/BinInterface/analyze.h:1.1 llvm/lib/Reoptimizer/BinInterface/analyze.h:1.2
--- llvm/lib/Reoptimizer/BinInterface/analyze.h:1.1	Fri Nov  8 04:38:12 2002
+++ llvm/lib/Reoptimizer/BinInterface/analyze.h	Tue Nov 12 20:44:48 2002
@@ -1,28 +1,29 @@
-//*****************************************************************************
+//===-----------------------------------------------------------*- C++ -*--===//
 //                          SPARC Instruction Analyzer
 //
 //  Definitions of Analysis API
 //
 // 2002 Cameron Buschardt
-//*****************************************************************************
-
-#ifndef __ANALYZE__
-#define __ANALYZE__
-
-#define IF_RS1  1			// READ from RS1
-#define IF_RS2  2			// READ from RS2
-#define IF_RD   4   		// WRITE to RC
-#define IF_BR   8			// BRANCH
-#define IF_WCC  16			// write to condition code
-#define IF_RCC  32			// read from condition code
-#define IF_USR  64          // first user IF instr
-
-// parse instruction
-unsigned sparc_analyze(unsigned instr);
-
-// use these command to expand the information return by analyze
+//===----------------------------------------------------------------------===//
+
+#ifndef __ANALYZE__
+#define __ANALYZE__
+
+#define IF_RS1  1           // READ from RS1
+#define IF_RS2  2           // READ from RS2
+#define IF_RD   4           // WRITE to RC
+#define IF_BR   8           // BRANCH
+#define IF_WCC  16          // write to condition code
+#define IF_RCC  32          // read from condition code
+#define IF_USR  64          // first user IF instr
+
+// parse instruction
+unsigned sparc_analyze(unsigned instr);
+
+// use these command to expand the information return by analyze
 unsigned sparc_getwrites(unsigned mask, unsigned instr);
 unsigned sparc_getreads (unsigned mask, unsigned instr);
-unsigned sparc_getcc    (unsigned mask, unsigned instr); // returns a bitmask containing RCC or WCC
-
-#endif
\ No newline at end of file
+// returns a bitmask containing RCC or WCC
+unsigned sparc_getcc    (unsigned mask, unsigned instr);
+
+#endif





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