[llvm-commits] CVS: llvm/lib/Reoptimizer/BinInterface/sparc9.h
Misha Brukman
brukman at neo.cs.uiuc.edu
Tue Nov 12 20:39:01 PST 2002
Changes in directory llvm/lib/Reoptimizer/BinInterface:
sparc9.h updated: 1.3 -> 1.4
---
Log message:
Manually converted the binary constants to hex, this way we don't need to have
a preprocessor for it (is that some Windows thing?). The original binary codes
are left in comments, digits grouped in fours to easily check if I went wrong
somewhere. Feel free to triple check as I only double-checked it. :)
---
Diffs of the changes:
Index: llvm/lib/Reoptimizer/BinInterface/sparc9.h
diff -u llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.3 llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.4
--- llvm/lib/Reoptimizer/BinInterface/sparc9.h:1.3 Fri Nov 8 04:38:13 2002
+++ llvm/lib/Reoptimizer/BinInterface/sparc9.h Tue Nov 12 20:40:00 2002
@@ -1,22 +1,22 @@
-//*****************************************************************************
+//===-----------------------------------------------------------*- C++ -*--===//
//
-// Portable SPARC v9 Machine Code Definition Header
+// Portable SPARC v9 Machine Code Definition Header
//
//
// 2002 Cameron Buschardt
-//*****************************************************************************
+//===----------------------------------------------------------------------===//
//*********************************
-// Bitfield manipulation Macros
+// Bitfield manipulation Macros
//*********************************
#define FLD_UPPER(FLD_DEF) (1 ? FLD_DEF)
#define FLD_LOWER(FLD_DEF) (0 ? FLD_DEF)
-#define MASKBELOW(V) ((1 << V) | ((1 << V) - 1)) //masks off everything ABOVE
+#define MASKBELOW(V) ((1 << V) | ((1 << V) - 1)) //masks off everything ABOVE
#define RD_FLD(x, FLD) ((x & MASKBELOW(FLD_UPPER(FLD))) >> FLD_LOWER(FLD))
#define MK_FLD(FLD, val) ((val << FLD_LOWER(FLD)) & MASKBELOW(FLD_UPPER(FLD)))
//**********************************
-// Portable sign extend macros
+// Portable sign extend macros
//**********************************
#define SIGN_EXTEND13(x) (x & 0x1000 ? -(-x & 0x1FFF): x)
#define SIGN_EXTEND(x, bits) (x & (1 << (bits-1)) ? -(-x & ((1 << bits)-1)):x)
@@ -24,46 +24,46 @@
//**********************************
// Instruction bitfield definitions
//**********************************
-#define INSTR_OP 31:30
-#define INSTR_A 29:29
-#define INSTR_FCN 29:25
-#define INSTR_DISP30 29:0
-#define INSTR_COND_H 28:25
-#define INSTR_RCOND_H 27:25
-#define INSTR_CC1_H 26:26
-#define INSTR_CC0_H 25:25
-#define INSTR_OP2 24:22
-#define INSTR_OP3 24:19
-#define INSTR_CC1_L 21:21
-#define INSTR_D16HI 21:20
-#define INSTR_D16LO 13:0
-#define INSTR_IMM22 21:0
-#define INSTR_DISP22 21:0
-#define INSTR_CC0_L 20:20
-#define INSTR_P 19:19
-#define INSTR_CC2 18:18
-#define INSTR_DISP19 18:0
-#define INSTR_IMPLDEP 18:0
-#define INSTR_COND_L 17:14
-#define INSTR_I 13:13
-#define INSTR_OPFCC 13:11
-#define INSTR_OPF 13:5
-#define INSTR_X 12:12
-#define INSTR_RCOND_L 12:10
-#define INSTR_IMMASI 12:5
-#define INSTR_SIMM13 12:0
-#define INSTR_OPFLOW_B 10:5
-#define INSTR_OPFLOW_S 9:5
-#define INSTR_SIMM10 9:0
-#define INSTR_CMASK 6:4
-#define INSTR_SWTRAP 6:0
-#define INSTR_SHCNT64 5:0
-#define INSTR_SHCNT32 4:0
-#define INSTR_MMASK 3:0
-
-#define INSTR_RS1 18:14
-#define INSTR_RS2 4:0
-#define INSTR_RD 29:25
+#define INSTR_OP 31:30
+#define INSTR_A 29:29
+#define INSTR_FCN 29:25
+#define INSTR_DISP30 29:0
+#define INSTR_COND_H 28:25
+#define INSTR_RCOND_H 27:25
+#define INSTR_CC1_H 26:26
+#define INSTR_CC0_H 25:25
+#define INSTR_OP2 24:22
+#define INSTR_OP3 24:19
+#define INSTR_CC1_L 21:21
+#define INSTR_D16HI 21:20
+#define INSTR_D16LO 13:0
+#define INSTR_IMM22 21:0
+#define INSTR_DISP22 21:0
+#define INSTR_CC0_L 20:20
+#define INSTR_P 19:19
+#define INSTR_CC2 18:18
+#define INSTR_DISP19 18:0
+#define INSTR_IMPLDEP 18:0
+#define INSTR_COND_L 17:14
+#define INSTR_I 13:13
+#define INSTR_OPFCC 13:11
+#define INSTR_OPF 13:5
+#define INSTR_X 12:12
+#define INSTR_RCOND_L 12:10
+#define INSTR_IMMASI 12:5
+#define INSTR_SIMM13 12:0
+#define INSTR_OPFLOW_B 10:5
+#define INSTR_OPFLOW_S 9:5
+#define INSTR_SIMM10 9:0
+#define INSTR_CMASK 6:4
+#define INSTR_SWTRAP 6:0
+#define INSTR_SHCNT64 5:0
+#define INSTR_SHCNT32 4:0
+#define INSTR_MMASK 3:0
+
+#define INSTR_RS1 18:14
+#define INSTR_RS2 4:0
+#define INSTR_RD 29:25
#define RD_D16(i) ((RD_FLD(i, INSTR_D16HI) << 14) | RD_FLD(i, INSTR_D16LO))
@@ -72,96 +72,99 @@
//**********************************
// Op-code classification
//**********************************
-#define OP_CALL 0b01
-#define OP_BRANCH 0b00
-#define OP_2 0b10
-#define OP_3 0b11
+#define OP_BRANCH 0x0 // 0b00
+#define OP_CALL 0x1 // 0b01
+#define OP_2 0x2 // 0b10
+#define OP_3 0x3 // 0b11
//**********************************
// Branch Class Instructions
//**********************************
-#define OP2_ILLTRAP 0b000 //OP=OP_BRANCH
-#define OP2_NOP 0b100 //BRANCH
-#define OP2_SETHI 0b100 //BRANCH - uhh? duplicate? DOH =p
-#define OP2_BICC 0b010
-#define OP2_BPR 0b011
-#define OP2_FB 0b110
-#define OP2_FBP 0b101
+#define OP2_ILLTRAP 0x0 // 0b000 //OP=OP_BRANCH
+#define OP2_BICC 0x2 // 0b010
+#define OP2_BPR 0x3 // 0b011
+#define OP2_NOP 0x4 // 0b100 //BRANCH
+#define OP2_SETHI 0x4 // 0b100 //BRANCH - uhh? duplicate? DOH =p
+#define OP2_FBP 0x5 // 0b101
+#define OP2_FB 0x6 // 0b110
//**********************************
// Register Condition Codes
//**********************************
-#define RCOND_RZ 0b001
-#define RCOND_RLEZ 0b010
-#define RCOND_RNZ 0b101
-#define RCOND_RGZ 0b110
-#define RCOND_RGEZ 0b111
+#define RCOND_RZ 0x1 // 0b001
+#define RCOND_RLEZ 0x2 // 0b010
+#define RCOND_RNZ 0x5 // 0b101
+#define RCOND_RGZ 0x6 // 0b110
+#define RCOND_RGEZ 0x7 // 0b111
//**********************************
// FPU Branch Conditions
//**********************************
-#define COND_FBN 0b0000
-#define COND_FBNE 0b0001
-#define COND_FBLG 0b0010
-#define COND_FBUL 0b0011
-#define COND_FBL 0b0100
-#define COND_FBUG 0b0101
-#define COND_FBG 0b0110
-#define COND_FBU 0b0111
-#define COND_FBA 0b1000
-#define COND_FBE 0b1001
-#define COND_FBUE 0b1010
-#define COND_FBGE 0b1011
-#define COND_FBUGE 0b1100
-#define COND_FBLE 0b1101
-#define COND_FBULE 0b1110
-#define COND_FBO 0b1111
+#define COND_FBN 0x0 // 0b0000
+#define COND_FBNE 0x1 // 0b0001
+#define COND_FBLG 0x2 // 0b0010
+#define COND_FBUL 0x3 // 0b0011
+#define COND_FBL 0x4 // 0b0100
+#define COND_FBUG 0x5 // 0b0101
+#define COND_FBG 0x6 // 0b0110
+#define COND_FBU 0x7 // 0b0111
+#define COND_FBA 0x8 // 0b1000
+#define COND_FBE 0x9 // 0b1001
+#define COND_FBUE 0xa // 0b1010
+#define COND_FBGE 0xb // 0b1011
+#define COND_FBUGE 0xc // 0b1100
+#define COND_FBLE 0xd // 0b1101
+#define COND_FBULE 0xe // 0b1110
+#define COND_FBO 0xf // 0b1111
//**********************************
// Integer Branch Conditions
//**********************************
-#define COND_BN 0b0000
-#define COND_BE 0b0001
-#define COND_BLE 0b0010
-#define COND_BL 0b0011
-#define COND_BLEU 0b0100
-#define COND_BCS 0b0101
-#define COND_BNEG 0b0110
-#define COND_BVS 0b0111
-#define COND_BA 0b1000
-#define COND_BNE 0b1001
-#define COND_BG 0b1010
-#define COND_BGE 0b1011
-#define COND_BGU 0b1100
-#define COND_BCC 0b1101
-#define COND_BPOS 0b1110
-#define COND_BVC 0b1111
+#define COND_BN 0x0 // 0b0000
+#define COND_BE 0x1 // 0b0001
+#define COND_BLE 0x2 // 0b0010
+#define COND_BL 0x3 // 0b0011
+#define COND_BLEU 0x4 // 0b0100
+#define COND_BCS 0x5 // 0b0101
+#define COND_BNEG 0x6 // 0b0110
+#define COND_BVS 0x7 // 0b0111
+#define COND_BA 0x8 // 0b1000
+#define COND_BNE 0x9 // 0b1001
+#define COND_BG 0xa // 0b1010
+#define COND_BGE 0xb // 0b1011
+#define COND_BGU 0xc // 0b1100
+#define COND_BCC 0xd // 0b1101
+#define COND_BPOS 0xe // 0b1110
+#define COND_BVC 0xf // 0b1111
//**********************************
// Name Lookup tables
// index is Condition code
//**********************************
-static char * fcond_names[] = {"FBN","FBNE","FBLG","FBUL","FBL","FBUG","FBG","FBU","FBA","FBE",
- "FBUE","FBGE","FBUGE","FBLE","FBULE","FBO"};
+static char * fcond_names[] =
+ { "FBN", "FBNE", "FBLG", "FBUL", "FBL", "FBUG", "FBG", "FBU",
+ "FBA", "FBE", "FBUE", "FBGE", "FBUGE", "FBLE", "FBULE","FBO" };
+
+static char * icond_names[] =
+ { "BN", "BE", "BLE", "BL", "BLEU", "BCS", "BNEG", "BVS",
+ "BA", "BNE", "BG", "BGE", "BGU", "BCC", "BPOS", "BVC"};
-static char * icond_names[] = {"BN","BE","BLE","BL","BLEU","BCS","BNEG","BVS","BA","BNE","BG","BGE",
- "BGU","BCC","BPOS","BVC"};
-
-static char * rcond_names[] = {"r000", "RZ", "RLEZ", "r011", "r100", "RNZ", "RGZ", "RGEZ"};
+static char * rcond_names[] =
+ { "r000", "RZ", "RLEZ", "r011", "r100", "RNZ", "RGZ", "RGEZ" };
//**********************************
// Flag register encoding
//**********************************
-#define FLAG_FCC0 0b000
-#define FLAG_FCC1 0b001
-#define FLAG_FCC2 0b010
-#define FLAG_FCC3 0b011
-#define FLAG_ICC 0b100
-#define FLAG_XCC 0b110
+#define FLAG_FCC0 0x0 // 0b000
+#define FLAG_FCC1 0x1 // 0b001
+#define FLAG_FCC2 0x2 // 0b010
+#define FLAG_FCC3 0x3 // 0b011
+#define FLAG_ICC 0x4 // 0b100
+#define FLAG_XCC 0x6 // 0b110
//**********************************
// OP_2 class instructions
@@ -169,143 +172,145 @@
// present members:
// RD, OP3, RS1
// if I=0
-// RS2
+// RS2
// else
-// SIMM13
+// SIMM13
//**********************************
-#define OP3_ADD 0b000000
-#define OP3_ADDC 0b001000
-#define OP3_AND 0b000001
-#define OP3_OR 0b000010
-#define OP3_XOR 0b000011
-#define OP3_SUB 0b000100
-#define OP3_ANDN 0b000101
-#define OP3_ORN 0b000110
-#define OP3_XNOR 0b000111
-#define OP3_SUBC 0b001100
-#define OP3_ADDcc 0b010000
-#define OP3_ADDCcc 0b011000
-#define OP3_ANDcc 0b010001
-#define OP3_ORcc 0b010010
-#define OP3_XORcc 0b010011
-#define OP3_SUBcc 0b010100
-#define OP3_ANDNcc 0b010101
-#define OP3_ORNcc 0b010110
-#define OP3_XNORcc 0b010111
-#define OP3_SUBCcc 0b011100
-#define OP3_MULX 0b001001
-#define OP3_SDIVX 0b101101
-#define OP3_UDIVX 0b001101
+#define OP3_ADD 0x0 // 0b00 0000
+#define OP3_ADDC 0x8 // 0b00 1000
+#define OP3_AND 0x1 // 0b00 0001
+#define OP3_OR 0x2 // 0b00 0010
+#define OP3_XOR 0x3 // 0b00 0011
+#define OP3_SUB 0x4 // 0b00 0100
+#define OP3_ANDN 0x5 // 0b00 0101
+#define OP3_ORN 0x6 // 0b00 0110
+#define OP3_XNOR 0x7 // 0b00 0111
+#define OP3_SUBC 0xc // 0b00 1100
+#define OP3_ADDcc 0x10 // 0b01 0000
+#define OP3_ADDCcc 0x18 // 0b01 1000
+#define OP3_ANDcc 0x11 // 0b01 0001
+#define OP3_ORcc 0x12 // 0b01 0010
+#define OP3_XORcc 0x13 // 0b01 0011
+#define OP3_SUBcc 0x14 // 0b01 0100
+#define OP3_ANDNcc 0x15 // 0b01 0101
+#define OP3_ORNcc 0x16 // 0b01 0110
+#define OP3_XNORcc 0x17 // 0b01 0111
+#define OP3_SUBCcc 0x1c // 0b01 1100
+#define OP3_MULX 0x9 // 0b00 1001
+#define OP3_SDIVX 0x2d // 0b10 1101
+#define OP3_UDIVX 0xd // 0b00 1101
//Op3 members
-#define OP3_CASA 0b111100
-#define OP3_CASXA 0b111110
+#define OP3_CASA 0x3c // 0b11 1100
+#define OP3_CASXA 0x3e // 0b11 1110
//Instructions below generated with:
//OP=OP_2: RD, OP_3 RS1: {I=0 -> X & RS2 ,I=1 -> {X=0 -> SHCNT32 X=1->SHCNT64 }}
-#define OP3_SLL 0b100101
-#define OP3_SRL 0b100110
-#define OP3_SRA 0b100111
+#define OP3_SLL 0x25 // 0b10 0101
+#define OP3_SRL 0x26 // 0b10 0110
+#define OP3_SRA 0x27 // 0b10 0111
// class OP_3
-#define OP3_STFA 0b110100
-#define OP3_STDFA 0b110111
-#define OP3_STQFA 0b110110
+#define OP3_STFA 0x34 // 0b11 0100
+#define OP3_STDFA 0x37 // 0b11 0111
+#define OP3_STQFA 0x36 // 0b11 0110
//Instructions below generated with:
//OP=OP_2: FCN
-#define OP3_DONERETRY 0b111110
-#define FCN_DONE 0
-#define FCN_RETRY 1
+#define OP3_DONERETRY 0x3e // 0b11 1110
+#define FCN_DONE 0
+#define FCN_RETRY 1
//These masks are valid for the instructions below
-#define OPF_MASK_ONs 0b0001 //these are valid for 'n' field
-#define OPF_MASK_ONd 0b0010
-#define OPF_MASK_ONq 0b0011
-#define OPF_MASK_TOs 0b0100 //these are valid for 't' field
-#define OPF_MASK_TOd 0b1000
-#define OPF_MASK_TOq 0b1100
+#define OPF_MASK_ONs 0x1 // 0b0001 //these are valid for 'n' field
+#define OPF_MASK_ONd 0x2 // 0b0010
+#define OPF_MASK_ONq 0x3 // 0b0011
+#define OPF_MASK_TOs 0x4 // 0b0100 //these are valid for 't' field
+#define OPF_MASK_TOd 0x8 // 0b1000
+#define OPF_MASK_TOq 0xc // 0b1100
-#define OPF_MASK_ON 0b0011
-#define OPF_MASK_TO 0b1100
+#define OPF_MASK_ON 0x3 // 0b0011
+#define OPF_MASK_TO 0xc // 0b1100
//Instructions below generated with
//OP=OP_2: CC1_H, CC0_H, RS1, OPF, RS2
-#define OP3_FCMP 0b110101
-#define OPF_FCMPn 0b001010000
-#define OPF_FCMPEn 0b001010100
+#define OP3_FCMP 0x35 // 0b 11 0101
+#define OPF_FCMPn 0x50 // 0b0 0101 0000
+#define OPF_FCMPEn 0x54 // 0b0 0101 0100
//Instructions below generated with
//OP=OP_2: RD, OP3 RS1, OPF, RS2
-#define OP3_FPU 0b110100
-#define OPF_FADDn 0b001000000
-#define OPF_FSUBn 0b001000100
-#define OPF_FMOVn 0b000000000
-#define OPF_FNEGn 0b000000100
-#define OPF_FABSn 0b000001000
-#define OPF_FMULn 0b001001000
-#define OPF_FDIVn 0b001001100
-#define OPF_FSQRTn 0b000101000
-#define OPF_FsTOx 0b010000001
-#define OPF_FsTOi 0b011010001
-#define OPF_FsTOd 0b011001001
-#define OPF_FsTOq 0b011001101
-#define OPF_FdTOx 0b010000010
-#define OPF_FdTOi 0b011010010
-#define OPF_FdTOs 0b011000110
-#define OPF_FdTOq 0b011001110
-#define OPF_FqTOx 0b010000011
-#define OPF_FqTOi 0b011010011
-#define OPF_FqTOs 0b011000111
-#define OPF_FqTOd 0b011001011
-#define OPF_FxTOt 0b010000000
-#define OPF_FiTOt 0b011000000
-#define OPF_FsMULd 0b001101001
-#define OPF_FdMULq 0b001101110
-
-
-#define OP3_FLUSH 0b111011 //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
-#define OP3_FLUSHW 0b101011 //OP=OP_2 I = 0
-#define OP3_JMPL 0b111000 //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
-#define OP3_LDFA 0b110000 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDDFA 0b110011 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-#define OP3_LDQFA 0b110010 //OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
-
-#define OP3_LDSTUB 0b001101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
-#define OP3_STB 0b000101
-#define OP3_STH 0b000110
-#define OP3_STW 0b000100
-#define OP3_STX 0b000111
-#define OP3_LDSB 0b001001
-#define OP3_LDSH 0b001010
-#define OP3_LDSW 0b001000
-#define OP3_LDUB 0b000001
-#define OP3_LDUH 0b000010
-#define OP3_LDUW 0b000000
-#define OP3_LDX 0b001011
-
-
-
-#define OP3_LDSTUBA 0b011101 //OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
-
-#define OP3_MEMBAR 0b101000 //OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set
+#define OP3_FPU 0x34 // 0b 11 0100
+#define OPF_FADDn 0x40 // 0b0 0100 0000
+#define OPF_FSUBn 0x44 // 0b0 0100 0100
+#define OPF_FMOVn 0x0 // 0b0 0000 0000
+#define OPF_FNEGn 0x4 // 0b0 0000 0100
+#define OPF_FABSn 0x8 // 0b0 0000 1000
+#define OPF_FMULn 0x48 // 0b0 0100 1000
+#define OPF_FDIVn 0x4c // 0b0 0100 1100
+#define OPF_FSQRTn 0x28 // 0b0 0010 1000
+#define OPF_FsTOx 0x81 // 0b0 1000 0001
+#define OPF_FsTOi 0xd1 // 0b0 1101 0001
+#define OPF_FsTOd 0xc9 // 0b0 1100 1001
+#define OPF_FsTOq 0xcd // 0b0 1100 1101
+#define OPF_FdTOx 0x82 // 0b0 1000 0010
+#define OPF_FdTOi 0xd2 // 0b0 1101 0010
+#define OPF_FdTOs 0xc6 // 0b0 1100 0110
+#define OPF_FdTOq 0xce // 0b0 1100 1110
+#define OPF_FqTOx 0x83 // 0b0 1000 0011
+#define OPF_FqTOi 0xd3 // 0b0 1101 0011
+#define OPF_FqTOs 0xc7 // 0b0 1100 0111
+#define OPF_FqTOd 0xcb // 0b0 1100 1011
+#define OPF_FxTOt 0x80 // 0b0 1000 0000
+#define OPF_FiTOt 0xc0 // 0b0 1100 0000
+#define OPF_FsMULd 0x69 // 0b0 0110 1001
+#define OPF_FdMULq 0x6e // 0b0 0110 1110
+
+
+#define OP3_FLUSH 0x3b // 0b11 1011 //OP=OP_2 RS1 {I=0 -> rs2, I=1->simm13}
+#define OP3_FLUSHW 0x2b // 0b10 1011 //OP=OP_2 I = 0
+#define OP3_JMPL 0x38 // 0b11 1000 //OP=OP_2 RD, RS1 {I=0-> RS2, I=1->SIMM13}
+//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+#define OP3_LDFA 0x30 // 0b11 0000
+//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+#define OP3_LDDFA 0x33 // 0b11 0011
+//OP=OP_3 RD, Rs1, {I=0->IMM_ASI, RS2 I=1->SIMM13}
+#define OP3_LDQFA 0x32 // 0b11 0010
+
+#define OP3_LDSTUB 0xd // 0b00 1101 //OP=OP_3 RD, Rs1 {I=0->RS2, I=1->SIMM13}
+#define OP3_STB 0x5 // 0b00 0101
+#define OP3_STH 0x6 // 0b00 0110
+#define OP3_STW 0x4 // 0b00 0100
+#define OP3_STX 0x7 // 0b00 0111
+#define OP3_LDSB 0x9 // 0b00 1001
+#define OP3_LDSH 0xa // 0b00 1010
+#define OP3_LDSW 0x8 // 0b00 1000
+#define OP3_LDUB 0x1 // 0b00 0001
+#define OP3_LDUH 0x2 // 0b00 0010
+#define OP3_LDUW 0x0 // 0b00 0000
+#define OP3_LDX 0xb // 0b00 1011
+
+
+//OP=OP_3 RD, RS1 {I=0->RS2, IMM_ASI, I=1->SIMM13}
+#define OP3_LDSTUBA 0x1d // 0b01 1101
+//OP=OP_2 CMASK, MMASK //WTF?!?! some bits get set
+#define OP3_MEMBAR 0x28 // 0b10 1000
//These two instructions are FUNKY as hell
-#define OP3_FMOVcc 0b110101 //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
-#define OP3_MOVcc 0b101100 //
-
+#define OP3_FMOVcc 0x35 // 0b11 0101 //OP=OP_2 RD, COND, OPF_CC, OPF_LOW, RS2
+#define OP3_MOVcc 0x2c // 0b10 1100 //
-#define OP3_POPC 0b101110
-#define OP3_PREFETCH 0b101101
-#define OP3_PREFETCHA 0b111101
-#define OP3_RETURN 0b111001
-#define OP3_SAVE 0b111100
-#define OP3_RESTORE 0b111101
-
-#define OP3_SAVDRESTD 0b110001
-#define FCN_SAVED 0
-#define FCN_RESTORED 1
-#define OP3_TRAP 0b111010 //integer trap
+#define OP3_POPC 0x2e // 0b10 1110
+#define OP3_PREFETCH 0x2d // 0b10 1101
+#define OP3_PREFETCHA 0x3d // 0b11 1101
+#define OP3_RETURN 0x39 // 0b11 1001
+#define OP3_SAVE 0x3c // 0b11 1100
+#define OP3_RESTORE 0x3d // 0b11 1101
+
+#define OP3_SAVDRESTD 0x31 // 0b11 0001
+#define FCN_SAVED 0
+#define FCN_RESTORED 1
+#define OP3_TRAP 0x3a // 0b11 1010 //integer trap
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