[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp X86InstrInfo.def

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.15 -> 1.16
X86InstrInfo.def updated: 1.7 -> 1.8

---
Log message:

Implement unconditional branching support


---
Diffs of the changes:

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.15 llvm/lib/Target/X86/InstSelectSimple.cpp:1.16
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.15	Fri Nov  1 19:41:55 2002
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Sat Nov  2 13:27:56 2002
@@ -55,6 +55,7 @@
     // fixed X86 code for each instruction.
     //
     void visitReturnInst(ReturnInst &RI);
+    void visitBranchInst(BranchInst &BI);
     void visitAdd(BinaryOperator &B);
     void visitShiftInst(ShiftInst &I);
 
@@ -161,6 +162,14 @@
   // block
   BuildMI(BB, X86::RET, 0);
 }
+
+void ISel::visitBranchInst(BranchInst &BI) {
+  if (BI.isConditional())   // Only handles unconditional branches so far...
+    visitInstruction(BI);
+
+  BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
+}
+
 
 /// Shift instructions: 'shl', 'sar', 'shr' - Some special cases here
 /// for constant immediate shift values, and for constant immediate


Index: llvm/lib/Target/X86/X86InstrInfo.def
diff -u llvm/lib/Target/X86/X86InstrInfo.def:1.7 llvm/lib/Target/X86/X86InstrInfo.def:1.8
--- llvm/lib/Target/X86/X86InstrInfo.def:1.7	Thu Oct 31 17:03:59 2002
+++ llvm/lib/Target/X86/X86InstrInfo.def	Sat Nov  2 13:27:56 2002
@@ -33,8 +33,9 @@
 // The second instruction must always be the noop instruction: (FIXME, not yet)
 I(NOOP        , "nop",                0, X86II::Void) // nop          90
 
-// Miscellaneous instructions
+// Flow control instructions
 I(RET         , "ret",       M_RET_FLAG, X86II::Void) // ret          CB
+I(JMP         , "jmp",    M_BRANCH_FLAG, X86II::Void) // jmp foo      EB|E9 cb|w
 
 // Move instructions
 I(MOVrr8      , "movb",               0, 0)           // R8  = R8     88/r