[llvm-commits] CVS: llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp PhyRegAlloc.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/RegAlloc:

LiveRangeInfo.cpp updated: 1.32 -> 1.33
PhyRegAlloc.cpp updated: 1.83 -> 1.84

---
Log message:

Rename the redundant MachineOperand::getOperandType() to MachineOperand::getType()



---
Diffs of the changes:

Index: llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
diff -u llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp:1.32 llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp:1.33
--- llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp:1.32	Sun Oct 27 20:28:38 2002
+++ llvm/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp	Sun Oct 27 22:45:27 2002
@@ -110,7 +110,7 @@
 
   // check if the LR is already there (because of multiple defs)
   if (!DefRange) { 
-    DefRange = this->createNewLiveRange(Def, isCC);
+    DefRange = createNewLiveRange(Def, isCC);
   } else {                          // live range already exists
     DefRange->insert(Def);          // add the operand to the range
     LiveRangeMap[Def] = DefRange;   // make operand point to merged set
@@ -134,7 +134,7 @@
   // first find the live ranges for all incoming args of the function since
   // those LRs start from the start of the function
   for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
-    this->createNewLiveRange(AI, /*isCC*/ false);
+    createNewLiveRange(AI, /*isCC*/ false);
 
   // Now suggest hardware registers for these function args 
   MRI.suggestRegs4MethodArgs(Meth, *this);
@@ -160,7 +160,7 @@
       // 
       if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
 	 TM.getInstrInfo().isCall(MInst->getOpCode()))
-	CallRetInstrList.push_back( MInst ); 
+	CallRetInstrList.push_back(MInst); 
  
       // iterate over explicit MI operands and create a new LR
       // for each operand that is defined by the instruction
@@ -168,9 +168,9 @@
              OpE = MInst->end(); OpI != OpE; ++OpI)
 	if (OpI.isDef()) {     
 	  const Value *Def = *OpI;
-          bool isCC = (OpI.getMachineOperand().getOperandType()
+          bool isCC = (OpI.getMachineOperand().getType()
                        == MachineOperand::MO_CCRegister);
-          this->createOrAddToLiveRange(Def, isCC);
+          createOrAddToLiveRange(Def, isCC);
 	}
 
       // iterate over implicit MI operands and create a new LR
@@ -178,7 +178,7 @@
       for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i) 
 	if (MInst->implicitRefIsDefined(i)) {     
 	  const Value *Def = MInst->getImplicitRef(i);
-          this->createOrAddToLiveRange(Def, /*isCC*/ false);
+          createOrAddToLiveRange(Def, /*isCC*/ false);
 	}
 
     } // for all machine instructions in the BB


Index: llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.83 llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.84
--- llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp:1.83	Sun Oct 27 20:28:39 2002
+++ llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp	Sun Oct 27 22:45:27 2002
@@ -539,8 +539,8 @@
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
         {
           MachineOperand& Op = MInst->getOperand(OpNum);
-          if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-              Op.getOperandType() ==  MachineOperand::MO_CCRegister)
+          if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+              Op.getType() ==  MachineOperand::MO_CCRegister)
             {
               const Value *const Val =  Op.getVRegValue();
           
@@ -750,7 +750,7 @@
                                      std::vector<MachineInstr*>& MIBef,
                                      std::vector<MachineInstr*>& MIAft) {
   
-  RegClass* RC = this->getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
+  RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
   
   int RegU =  getUnusedUniRegAtMI(RC, MInst, LVSetBef);
   
@@ -766,8 +766,8 @@
     int scratchRegType = -1;
     if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
       {
-        int scratchReg = this->getUsableUniRegAtMI(scratchRegType, LVSetBef,
-                                                   MInst, MIBef, MIAft);
+        int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
+                                             MInst, MIBef, MIAft);
         assert(scratchReg != MRI.getInvalidRegNum());
         
         // We may as well hold the value in the scratch register instead
@@ -893,8 +893,8 @@
     {
       const MachineOperand& Op = MInst->getOperand(OpNum);
       
-      if (Op.getOperandType() == MachineOperand::MO_VirtualRegister || 
-          Op.getOperandType() == MachineOperand::MO_CCRegister)
+      if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister || 
+          MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
         if (const Value* Val = Op.getVRegValue())
           if (MRI.getRegClassIDOfValue(Val) == RC->getID())
             if (Op.getAllocatedRegNum() == -1)
@@ -971,9 +971,9 @@
       for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
 	MachineOperand& Op = MInst->getOperand(OpNum);
 
-	if (Op.getOperandType() ==  MachineOperand::MO_VirtualRegister || 
-	    Op.getOperandType() ==  MachineOperand::MO_CCRegister /*|| 
-	    Op.getOperandType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
+	if (Op.getType() ==  MachineOperand::MO_VirtualRegister || 
+	    Op.getType() ==  MachineOperand::MO_CCRegister /*|| 
+	    Op.getType() ==  MachineOperand::MO_PCRelativeDisp*/ ) {
 
 	  const Value *const Val = Op.getVRegValue () ;
 	  // ****this code is temporary till NULL Values are fixed
@@ -1005,7 +1005,7 @@
 	  }
 
 	} 
-	else if (Op.getOperandType() ==  MachineOperand::MO_MachineRegister) {
+	else if (Op.getType() ==  MachineOperand::MO_MachineRegister) {
 	  cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
 	}