[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcOptInfo.cpp

[Vikram Adve]

Changes in directory llvm/lib/Target/Sparc:

SparcOptInfo.cpp updated: 1.2 -> 1.3

---
Log message:

Test both operands of ADD or OR for zero to find useless copies.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcOptInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.2 llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.3
--- llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.2	Fri Sep 27 09:30:49 2002
+++ llvm/lib/Target/Sparc/SparcOptInfo.cpp	Sat Oct 12 19:20:15 2002
@@ -29,19 +29,29 @@
     }
   else if (MI->getOpCode() == ADD || MI->getOpCode() == OR)
     {
-      return (/* operand 0 are operand 2 are allocated to the same register */
-              (MI->getOperand(0).getAllocatedRegNum() == 
-               MI->getOperand(2).getAllocatedRegNum()) &&
-              
-              (/* and: either operand 1 is register %g0 */
-               (MI->getOperand(1).hasAllocatedReg() &&
-                MI->getOperand(1).getAllocatedRegNum() ==
-                target.getRegInfo().getZeroRegNum()) ||
-               
-               /* or operand 1 == 0 */
-               (MI->getOperand(1).getOperandType()
-                == MachineOperand::MO_SignExtendedImmed &&
-                MI->getOperand(1).getImmedValue() == 0)));
+      unsigned srcWithDestReg;
+
+      for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
+        if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
+            MI->getOperand(srcWithDestReg).getAllocatedRegNum()
+            == MI->getOperand(2).getAllocatedRegNum())
+          break;
+
+      if (srcWithDestReg == 2)
+        return false;
+      else
+        {/* else source and dest are allocated to the same register */
+          unsigned otherOp = 1 - srcWithDestReg;
+          return (/* either operand otherOp is register %g0 */
+                  (MI->getOperand(otherOp).hasAllocatedReg() &&
+                   MI->getOperand(otherOp).getAllocatedRegNum() ==
+                   target.getRegInfo().getZeroRegNum()) ||
+                  
+                  /* or operand otherOp == 0 */
+                  (MI->getOperand(otherOp).getOperandType()
+                   == MachineOperand::MO_SignExtendedImmed &&
+                   MI->getOperand(otherOp).getImmedValue() == 0));
+        }
     }
   else
     return false;