[llvm-commits] CVS: llvm/lib/Target/Sparc/SparcOptInfo.cpp

[Vikram Adve]

Changes in directory llvm/lib/Target/Sparc:

SparcOptInfo.cpp updated: 1.1 -> 1.2

---
Log message:

Check for floating point copies (FMOVS, FMOVD).
Also handle add with constant 0, in addition to add with %g0.


---
Diffs of the changes:

Index: llvm/lib/Target/Sparc/SparcOptInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.1 llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.2
--- llvm/lib/Target/Sparc/SparcOptInfo.cpp:1.1	Fri Sep 20 11:38:35 2002
+++ llvm/lib/Target/Sparc/SparcOptInfo.cpp	Fri Sep 27 09:30:49 2002
@@ -11,8 +11,9 @@
 //----------------------------------------------------------------------------
 // Function: IsUselessCopy
 // Decide whether a machine instruction is a redundant copy:
-// -- add    with g0
-// -- or     with g0.
+// -- ADD    with g0 and result and operand are identical, or
+// -- OR     with g0 and result and operand are identical, or
+// -- FMOVS or FMOVD and result and operand are identical.
 // Other cases are possible but very rare that they would be useless copies,
 // so it's not worth analyzing them.
 //----------------------------------------------------------------------------
@@ -20,12 +21,28 @@
 bool
 UltraSparcOptInfo::IsUselessCopy(const MachineInstr* MI) const
 {
-  if (MI->getOpCode() != ADD && MI->getOpCode() != OR)
+  if (MI->getOpCode() == FMOVS || MI->getOpCode() == FMOVD)
+    {
+      return (/* both operands are allocated to the same register */
+              MI->getOperand(0).getAllocatedRegNum() == 
+              MI->getOperand(1).getAllocatedRegNum());
+    }
+  else if (MI->getOpCode() == ADD || MI->getOpCode() == OR)
+    {
+      return (/* operand 0 are operand 2 are allocated to the same register */
+              (MI->getOperand(0).getAllocatedRegNum() == 
+               MI->getOperand(2).getAllocatedRegNum()) &&
+              
+              (/* and: either operand 1 is register %g0 */
+               (MI->getOperand(1).hasAllocatedReg() &&
+                MI->getOperand(1).getAllocatedRegNum() ==
+                target.getRegInfo().getZeroRegNum()) ||
+               
+               /* or operand 1 == 0 */
+               (MI->getOperand(1).getOperandType()
+                == MachineOperand::MO_SignExtendedImmed &&
+                MI->getOperand(1).getImmedValue() == 0)));
+    }
+  else
     return false;
-
-  return ((MI->getOperand(0).getAllocatedRegNum() == 
-           MI->getOperand(2).getAllocatedRegNum()) &&
-          (MI->getOperand(1).hasAllocatedReg() &&
-           MI->getOperand(1).getAllocatedRegNum() ==
-           target.getRegInfo().getZeroRegNum()));
 }