[llvm-bugs] [Bug 38898] New: LLVM ERROR: Use not jointly dominated by defs. after simple-register-coalescing

[via llvm-bugs]

https://bugs.llvm.org/show_bug.cgi?id=38898

            Bug ID: 38898
           Summary: LLVM ERROR: Use not jointly dominated by defs. after
                    simple-register-coalescing
           Product: new-bugs
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: NEW
          Severity: enhancement
          Priority: P
         Component: new bugs
          Assignee: unassignedbugs at nondot.org
          Reporter: mikael.holmen at ericsson.com
                CC: llvm-bugs at lists.llvm.org

Created attachment 20864
  --> https://bugs.llvm.org/attachment.cgi?id=20864&action=edit
reproducer

Reproduce with
 llc -o - coalesce.mir -march=amdgcn -run-pass simple-register-coalescing
-verify-machineinstrs

which gives

Use of $noreg does not have a corresponding definition on every path:
48r %2.sub0:sreg_64 = IMPLICIT_DEF
LLVM ERROR: Use not jointly dominated by defs.

-debug shows

...
0B      bb.0:
          successors: %bb.1(0x80000000); %bb.1(100.00%)

16B       %0:sreg_32 = IMPLICIT_DEF
32B       %1:sreg_32 = IMPLICIT_DEF
48B       undef %2.sub0:sreg_64 = IMPLICIT_DEF
64B       %2.sub1:sreg_64 = COPY %1:sreg_32
...

...
64B     %2.sub1:sreg_64 = COPY %1:sreg_32
        Considering merging to SReg_64 with %1 in %2:sub1
                RHS = %1 [32r,64r:0)  0 at 32r weight:0.000000e+00
                LHS = %2
[16r,48r:1)[48r,64r:2)[64r,80B:4)[80B,112B:6)[128r,144r:0)[144r,176B:3)[176B,240r:5)
 0 at 128r 1 at 16r 2 at 48r 3 at 144r 4 at 64r 5 at 176B-phi 6 at 80B-phi L00000001
[48r,80B:1)[80B,112B:3)[128r,176B:0)[176B,224r:2)  0 at 128r 1 at 48r 2 at 176B-phi
3 at 80B-phi L00000002 [64r,80B:2)[80B,112B:4)[144r,176B:0)[176B,240r:3)  0 at 144r
1 at x 2 at 64r 3 at 176B-phi 4 at 80B-phi weight:0.000000e+00
...
                erased: 16r     undef %2.sub1:sreg_64 = IMPLICIT_DEF
                erased: 64r     %2.sub1:sreg_64 = COPY %1:sreg_32
                erased: 32r     %1:sreg_32 = IMPLICIT_DEF
...

So we end up with this bb.0:

0B      bb.0:
         successors: %bb.1(0x80000000); %bb.1(100.00%)

48B      %2.sub0:sreg_64 = IMPLICIT_DEF


Originally found when compiling for an out-of-tree target.

Thanks to Matthias Braun for the above AMDGPU reproducer.

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